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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

共 1035 条记录，以下是401-410 订阅

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Clearing the clutter: Unified modeling and verification methodology for system level hardware design

Clearing the clutter: Unified modeling and verification meth...

引用

acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Yosinori Watanabe Stuart Swan Cadence Design Systems Berkeley CA USA Cadence Design Systems San Jose CA USA

The state-of-the-art design practice for complex SoCs employs multiple models of hardware components with different use cases. The cost of building and maintaining those models is high, and verifying the consistency among those models is time consuming. This paper highlights needs and issues of creating these models, and presents emerging approaches for developing solutions to address the issues.

关键词： hardware software Computational modeling system-on-a-chip Timing Clutter Solid modeling

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MEMOCODE 2012 hardware/software codesign contest: DNA sequence aligner

MEMOCODE 2012 hardware/software codesign contest: DNA sequen...

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Stephen A. Edwards Department of Computer Science Columbia University New York NY USA

The MEMOCODE design contest for 2012 is exact substring matching: a simplified form of the DNA sequence alignment problem. The challenge is to efficiently locate millions of 100-base-pair short read sequences in a 3-million-base-pair reference genome. Contestants had a month to create a fast system that ran on a given set of test data. Entries were judged both on absolute time and the product of time and system cost. The two winning groups, which were invited to contribute papers describing their solutions, judiciously chose algorithms that exploited powerful hardware. The two winning entries employed a hash algorithm running on a Convey HC-1 FPGA/multicore hybrid with an aggressive memory system and a Burrows-Wheeler/hash hybrid running on a 12-core Intel system was second.

关键词： Genomics Bioinformatics DNA Educational institutions Humans Runtime Indexes

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Shepard: A fast exact match short read aligner

Shepard: A fast exact match short read aligner

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Chad Nelson Kevin Townsend Bhavani Satyanarayana Rao Phillip Jones Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Ames IA USA

The mapping of many short sequences of DNA, called reads, to a long reference genome is an common task in molecular biology. The task amounts to a simple string search, allowing for a few mismatches due to mutations and inexact read quality. While existing solutions attempt to align a high percentage of the reads using small memory footprints, Shepard is concerned with only exact matches and speed. Using the human genome, Shepard is on the order of hundreds of thousands of times faster than current software implementations such as SOAP2 or Bowtie, and about 60 times faster than GPU implementations such as SOAP3. Shepard contains two components: a software program to preprocess a reference genome into a hash table, and a hardware pipeline for performing fast lookups. The hash table has one entry for each unique 100 base pair sequence that occurs in the reference genome, and contains the index of last occurrence and the number of occurrences. To reduce the hash table size, a minimal perfect hash table is used. The hardware pipeline was designed to perform hash table lookups very quickly, on the order of 600 million lookups per second, and was implemented on a Convey HC-1 high performance reconfigurable computing system. Shepard streams all of the short reads through a custom hardware pipeline and writes the alignment data (index of last occurrence and number of occurrences) to a binary results array.

关键词： Bioinformatics Genomics hardware Indexes Pipelines DNA Coprocessors

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Reliable software for unreliable hardware: Embedded code generation aiming at reliability 11

Reliable software for unreliable hardware: Embedded code gen...

引用

Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/acm international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Rehman, Semeen Shafique, Muhammad Kriebel, Florian Henkel, Jörg Karlsruhe Germany

ISBN: (纸本)9781450307154

A compilation technique for reliability-aware software transformations is presented. An instruction-level reliability estimation technique quantifies the effects of hardware-level faults at the instruction-level while considering spatial and temporal vulnerabilities. It bridges the gap between hardware - where faults occur according to our fault model - and software (the abstraction level where we aim to increase reliability). For a given tolerable performance overhead, an optimization algorithm compiles an application software with respect to a tradeoff between performance and reliability. Compared to performance-optimized compilation, our method incurs 60%-80% lower application failures, averaged over various fault injection scenarios and fault rates. Copyright 2011 acm.

关键词： Embedded systems

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A design methodology to implement memory accesses in high-level synthesis 11

A design methodology to implement memory accesses in high-le...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/acm international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Pilato, Christian Ferrandi, Fabrizio Sciuto, Donatella Dipartimento di Elettronica ed Informazione Politecnico di Milano Milano 20133 Italy

ISBN: (纸本)9781450307154

Nowadays, the memory synthesis is becoming the main bottleneck for the generation of efficient hardware accelerators. This paper presents a design methodology to efficiently and automatically implement memory accesses in High-Level synthesis. In particular, the approach starts from a behavioral specification (in pure C language) and a set of design constraints, such as the memory addresses where some of the data are stored. The methodology classifies which variables can be internally or externally allocated to the different modules to generate the proper architecture, fully supporting a wide range of C constructs, such as pointer arithmetic, function calls and array accesses. Moreover it allows to parallelize the accesses when the memory address is known at compile time, resulting in an efficient execution of the specification. Copyright 2011 acm.

关键词： High level synthesis

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system-level design space exploration for three-dimensional (3D) SoCs 11

System-level design space exploration for three-dimensional ...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/acm international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Zou, Qiaosha Chen, Yibo Xie, Yuan Su, Alan Computer Science and Engineering Pennsylvania State University United States Synopsys Inc. Hsinchu Taiwan

ISBN: (纸本)9781450307154

Three-dimensional (3D) ICs promise to overcome barriers in integration density and interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved performance, higher memory bandwidth, smaller form factors, and heterogeneous integration. 3D integration provides additional architectural and technology-related design options for future system-on-chip (SoC) designs, making the early design space exploration more critical. This paper proposes a system-level design partition and hardware/ software co-synthesis framework for 3D SoC integration. The proposed methodology can be used to explore the enlarged design space and to find out the optimal design choices for given design constraints including form factor, performance, power, or yield. Copyright 2011 acm.

关键词： system-on-chip

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system-level power and timing variability characterization to compute thermal guarantees 11

System-level power and timing variability characterization t...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/acm international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Kumar, Pratyush Thiele, Lothar Computer Engineering and Networks Laboratory ETH Zurich Switzerland

ISBN: (纸本)9781450307154

With ever-increasing power densities, temperature management using software and hardware techniques has become a necessity in the design of modern electronic systems. Such techniques have to be validated and optimized with respect to the thermal guarantee they provide, i.e., a safe upperbound on the peak temperature of the system under all operating conditions. The computation of such a guarantee depends on the power and timing characteristics of the system. In this paper, we present formalisms to capture such characteristics at the system-level and provide an analytical technique to compute a provably safe upper-bound on the peak temperature. The proposed characterization and analysis is general in that it considers an impulse-responsebased thermal model, task-dependent power consumption, tasks with dynamic arrival patterns and variable resource demand, and a scheduling policy expressed as a hierarchical composition of several commonly used policies. Copyright 2011 acm.

关键词： Timing circuits

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Branch penalty reduction on IBM cell SPUs via software branch hinting 11

Branch penalty reduction on IBM cell SPUs via software branc...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/acm international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Lu, Jing Kim, Yooseong Shrivastava, Aviral Huang, Chuan Compiler Microarchitecture Lab Arizona State University Tempe AZ 85281 United States

ISBN: (纸本)9781450307154

As power-efficiency becomes paramount concern in processor design, architectures are coming up that completely do away with hardware branch prediction, and rely solely on software branch hinting. A popular example is the Synergistic Processing Unit (SPU) in the IBM Cell processor. To be able to minimize the branch penalty using branch hint instructions, in addition to estimating the branch probabilities (which has been looked at before [6, 25, 24]), it is important to carefully insert branch hints. Towards this, in this paper, we i) construct a branch penalty model for compiler, ii) formulate the problem of minimizing branch penalty using branch hinting and iii) propose a heuristic to solve this problem. The heuristic is based on three basic techniques that we introduce in this paper: NOP padding, hint pipelining, and nested loop restructuring. Experimental results on several benchmarks show that our solution can reduce the branch penalty as much as 35.4% over the previous approach. Copyright 2011 acm.

关键词： Program compilers

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SoC-TM: Integrated HW/SW support for transactional memory programming on embedded MPSoCs 11

SoC-TM: Integrated HW/SW support for transactional memory pr...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/acm international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Ferri, Cesare Bahar, Iris. Marongiu, Andrea Benini, Luca Lipton, Benjamin Moreshet, Tali Herlihy, Maurice School of Engineering Brown University Providence RI 02912 United States DEIS University of Bologna Viale Risorgimento 2 40136 Bologna Italy Engineering Dept Swarthmore College Swarthmore PA 19081 United States Computer Science Dept Brown University Providence RI 02912 United States

ISBN: (纸本)9781450307154

Two overriding concerns in the development of embedded MPSoCs are ease of programming and hardware complexity. In this paper we present SoC-TM, an integrated HW/SW solution for transactional programming on embedded MP- SoCs. Our proposal leverages a hardware Transactional Memory (HTM) design, based on a dedicated HW module for conflict management, whose functionality is exposed to the software through compiler directives, implemented as an extension to the popular OpenMP programming model. To further improve ease of programming, our framework sup- ports speculative parallelism, thanks to the ability of enforcing a given commit order in hardware. Our experimental results confirm that SoC-TM is a viable and cost-effective solution for embedded MPSoCs, in terms of energy, performance and productivity. Copyright 2011 acm.

关键词： system-on-chip

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Dominator homomorphism based code matching for source-level simulation of embedded software 11

Dominator homomorphism based code matching for source-level ...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/acm international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Stattelmann, Stefan Bringmann, Oliver Rosenstiel, Wolfgang FZI Forschungszentrum Informatik Haid-und-Neu-Str. 10-14 D-76131 Karlsruhe Germany University of Tuebingen Sand 13 D-72076 Tuebingen Germany

ISBN: (纸本)9781450307154

Relating optimized binary code and the source-level statements from which it was created can be challenging if an optimizing compiler was used to create the machine code. Moreover, this relation is crucial if a compiler-optimized program must be debugged or results from a low-level analysis need to be mapped to the source code to perform manual optimizations. Existing approaches for the debugging of optimized code usually require pervasive changes in the compiler and hence are not available for all architectures. Methods for analyzing non-functional properties of software components in complex systems (i.e. execution time and power consumption) often have similar constraints, if compiler optimizations are supported at all. This paper proposes two novel concepts to overcome these issues. To precisely relate source-level statements with the respective compiler-generated machine code, a method to reconstruct and disambiguate debug information is presented. Based on this information, an instrumentation technique is introduced which allows accurately simulating the execution of optimized binary code at the source code level. Experimental results show that by using this technique, arbitrary low-level properties of software components can be evaluated in a fast and accurate manner without running the software on the actual target hardware. Copyright 2011 acm.

关键词： Binary codes

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