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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

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Constraint-driven synthesis and tool-support for flexray-based automotive control systems 11

Constraint-driven synthesis and tool-support for flexray-bas...

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Embedded systems Week 2011, ESWEEK 2011 - 9th IEEE/acm international conference on hardware/software-codesign and system synthesis, CODES+ISSS'11

作者： Schneider, Reinhard Goswami, Dip Zafar, Sohaib Chakraborty, Samarjit Lukasiewycz, Martin TU Munich Germany TUM CREATE Singapore

ISBN: (纸本)9781450307154

Emerging bus protocols such as FlexRay provide an expedient platform for the design of automotive control systems due to its high bandwidth and deterministic temporal behavior. However, the choice of suitable platform parameters such as task and message schedules becomes a challenging design problem as the protocol is complex in nature and enforces a tight coupling between local task schedules on ECUs and global bus schedules. Although there exist several commercial off-the-shelf (COTS) design tools for FlexRay and control systems, current tools do not provide any mechanism for automatically synthesizing the platform parameters from the controller specifications. In this work we synthesize controllers subject to specified control goals while taking into account platform-specific properties. In particular, we translate the timing constraints derived from the control design into platform constraints that need to be satisfied by the control-related tasks and messages. For this purpose, we formulate and solve a constraint satisfaction problem (CSP) to synthesize feasible platform parameters that can be realized by the underlying operating systems and the FlexRay bus. Our design flow may be easily integrated with existing FlexRay design tools and will significantly ease (and automate) the existing design process. We show the applicability of our results by implementing two automotive control systems on a hardware-in-the-Loop (HiL) setup and study how different bus configurations affect the controller synthesis and the choice of platform parameters. Copyright 2011 acm.

关键词： Cyber Physical system

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Rigorous system level modeling and analysis of mixed HW/SW systems 11

Rigorous system level modeling and analysis of mixed HW/SW s...

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Proceedings of the Ninth acm/IEEE international conference on Formal Methods and Models for codesign

作者： Bourgos, P. Basu, A. Bozga, M. Bensalem, S. Sifakis, J. Huang, K. UJF-Grenoble 1 / CNRS VERIMAG UMR 5104 Grenoble F-38041 France Institute of VLSI Design Zhejiang University China

ISBN: (纸本)9781457701160

A grand challenge in complex embedded systems design is developing methods and tools for modeling and analyzing the behavior of an application software running on multicore or distributed platforms. We propose a rigorous method and a tool chain that allows to obtain a faithful model representing the behavior of a mixed hardware/software system from a model of its application software and a model of its underlying hardware architecture. The system model can be simulated and analyzed for validation of both functional and extra-functional properties. The tool chain uses DOL (Distributed Operation Layer [1]) as the frontend for specifying the application software and hardware architecture, and BIP (Behavior Interaction Priority [2]) as the modeling and analysis framework. It is illustrated through the construction of system models of MJPEG and MPEG2 decoder applications running on MPARM, a multicore architecture. © 2011 IEEE.

关键词： Application programs

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Design entropy concept: A measurement for complexity 11

Design entropy concept: A measurement for complexity

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Benjamin Menhorn Frank Slomka Institute for Embedded Systems/Real-Time Systems Ulm University Germany

ISBN: (纸本)9781450307154

In general, this work will deal with measuring complexity. The focus question is towards addressing complexity in an adequate way. This work concentrates on digital circuits and digital hardware. For this field of computer science the complexity for circuits will be calculated. Therefore, a new complexity measure will be introduced, called design entropy. It allows a mathematical calculation of complexity resulting in figures. These allow a direct evaluation and comparison between different systems and realizations. The application and important capabilities of this measurement will be demonstrated on different examples.

关键词： Complexity theory Entropy Computer architecture hardware Microprocessors Mathematical model Transistors

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CODES+ISSS keynote: To alert, rescue and recover: Critical information technologies for managing mega disasters

CODES+ISSS keynote: To alert, rescue and recover: Critical i...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Jane W. S. Liu Institute of Information Science and Research Center for Information Technology Innovations Academia Sinica Taiwan

This talk will discuss why despite recent advances, state-of-the-art disaster management IT infrastructures and information systems are not as effective as they should be for managing mega calamitous events of unforeseen sizes and severity. It will then discuss critical gaps in information technology. Examples include methodologies, tools and middleware for: ▪ Exploitation of complementary network technologies to prevent communication failures during disasters; ▪ Flexible and responsive management of logical connectivity and information flow among information sources, fusion modules, applications and end-users, providing them with support for pub/sub messaging, syndication and feed services, dynamic event-triggered messaging and so on; ▪ Trustworthy information brokerage services for safe and responsive emergency access and flow control of information from independently developed information sources owned by government agencies, businesses, institutions, NGOs, communities, private property owners and individuals; ▪ Common models and views, open standard interfaces and API functions to enable independent development of disaster management applications and services; ▪ Advanced disaster management applications and services.

关键词： Information technology Information science Disaster management Real time systems Awards activities software Information systems

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IOPT Petri Net State Space Generation Algorithm with Maximal-Step Execution Semantics

IOPT Petri Net State Space Generation Algorithm with Maximal...

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9th IEEE international conference on Industrial Informatics (INDIN)

作者： Pereira, Fernando Moutinho, Filipe Gomes, Luis Campos-Rebelo, Rogerio ISEL Inst Super Engenharie Lisboa Lisbon Portugal Univ Nova Lisboa CTS Caparica Portugal

ISBN: (纸本)9781457704345

This paper presents an algorithm to efficiently generate the state-space of systems specified using the IOPT Petri-net modeling formalism. IOPT nets are a non-autonomous Petri-net class, based on Place-Transition nets with an extended set of features designed to allow the rapid prototyping and synthesis of system controllers through an existing hardware-software co-design framework. To obtain coherent and deterministic operation, IOPT nets use a maximal-step execution semantics where, in a single execution step, all enabled transitions will fire simultaneously. This fact increases the resulting state-space complexity and can cause an arc "explosion" effect. Real-world applications, with several million states, will reach a higher order of magnitude number of arcs, leading to the need for high performance state-space generator algorithms. The proposed algorithm applies a compilation approach to read a PNML file containing one IOPT model and automatically generate an optimized C program to calculate the corresponding state-space.

关键词： Algorithm design and analysis C language C program Fires Firing Generators IOPT Petri net generation algorithm IOPT Petri-net modeling formalism PNML file Petri nets Semantics software system recovery arc explosion effect compilation approach computational complexity formal verification hardware-software codesign framework input-output place-transition Petri nets maximal-step execution semantics model checking approach place-transition nets program compilers rapid prototyping state-space complexity

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Session details: Tools and algorithms for exploration and synthesis of distributed embedded systems 11

Session details: Tools and algorithms for exploration and sy...

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Proceedings of the seventh IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Hiroyuki Tomiyama Todor Stefanov Ritsumeikan University Leiden University

No abstract available.

ISBN: (纸本)9781450307154

No abstract available.

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MEMOCODE 2011 hardware/software codesign Contest: NoC simulator

MEMOCODE 2011 Hardware/Software CoDesign Contest: NoC simula...

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Derek Chiou University of Texas Austin USA

The objective of the 2011 MEMOCODE hardware software codesign Contest was to improve the performance of a configurable Network-on-Chip (NoC) simulator. A C++ reference simulator was provided, whose output was defined to be correct. The simulator takes two inputs: (i) a specification of the NoC to be simulated (the target) and (ii) a traffic pattern that specifies the traffic to be simulated on that NoC. The simulator was designed to support virtually any NoC topology. Results were judged firstly on correctness (that the number of cycles is accurately modeled) and secondly on simulation speed (the amount of time it takes to complete the entire simulation).

关键词： Delay Routing Data models hardware software Buffer storage system-on-a-chip

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Function interface models for hardware compilation

Function interface models for hardware compilation

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Dan R. Ghica University of Binningham UK

The problem of synthesis of gate-level descriptions of digital circuits from behavioural specifications written in higher-level programming languages (hardware compilation) has been studied for a long time yet a definitive solution has not been forthcoming. The emphasis of the first part of this tutorial is methodological, arguing that one of the major obstacles in the way of hardware compilation becoming a useful and mature technology is the lack of a well defined function interface model, i.e. a canonical way in which functions communicate with arguments. In the second part we present a solution based on the Geometry of synthesis, a semantics-directed approach to hardware compilation.

关键词： hardware Wires Syntactics hardware design languages software Logic gates

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Rigorous system level modeling and analysis of mixed HW/SW systems

Rigorous system level modeling and analysis of mixed HW/SW s...

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： P. Bourgos A. Basu M. Bozga S. Bensalem J. Sifakis K. Huang VERIMAG UMR 5104 UJF-Grenoble 1 / CNRS Grenoble France Institute of VLSI Design University of Zhejiang China

关键词： hardware Computer architecture Application software Program processors Analytical models Indexes

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system-level design exploration for 3-D stacked memory architectures 11

System-level design exploration for 3-D stacked memory archi...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Chi-Hung Lin Wen-Tsan Hsieh Hsien-Ching Hsieh Chun-Nan Liu Jen-Chieh Yeh Information and Communications Research Laboratories Industrial Technology Research Institute Hsinchu Taiwan

ISBN: (纸本)9781450307154

Summary form only given. Traditional technology scaling of semiconductor chips followed Moore's Law. However, the transistor performance improvement will be limited, and designer will not see doubling of frequency every two years. Recently, three-dimension integrated circuits (3D IC) that employ the vertically through-silicon vias (TSVs) for connecting each of dies have been proposed. It is an alternative solution to existent Package-on-Package (PoP) and system-in-Package (SiP) processes. There are many benefits by using TSV-based 3-D integration technologies: (1) more functionality can be integrated into a small silicon space for form factor reduction, (2) circuit delay can be improved by using TSVs due to the shorter interconnect and reduced parasitic capacitance/inductance, (3) different components with incompatible manufacturing process (i.e. Logic, DRAM, Flash, etc) can be combined in single 3-D IC for heterogeneous integration. In addition, there are many 3-D multi-core or many-core architectures are discussed recently. Comparing with traditional two-dimension multi-core or many-core architectures, the major difference is memory bandwidth problem can be addressed by stacked memory architecture. Intel has good demonstration through the teraflops microprocessor chip which is an 80-core design with memory-on-logic architecture. And, each core connects to a 256KB SRAM with 12GB/s bandwidth. Although 3-D stacking technology can bring us many benefits for next generation integrated circuits, it comes with many problems and challenges in system-level design. For instance, 3-D IC designs will deal with serious challenges in design space exploration and system validation. For most designs, the number of TSV will be the most critical limitation that should be considered carefully. Besides, system design by 3-D IC will become more and more complex, and it needs a full system-level solution to face the performance, number of TSV, and power issues of 3D-IC. Furthermore, it

关键词： Through-silicon vias Integrated circuit modeling Stacking Multicore processing Random access memory

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