检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

995 篇 会议
40 篇 期刊文献

馆藏范围

1,035 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

542 篇 工学
- 512 篇 计算机科学与技术...
- 403 篇 软件工程
- 109 篇 电气工程
- 103 篇 电子科学与技术（可...
- 48 篇 信息与通信工程
- 40 篇 控制科学与工程
- 26 篇 机械工程
- 12 篇 建筑学
- 11 篇 动力工程及工程热...
- 7 篇 材料科学与工程（可...
- 6 篇 光学工程
- 6 篇 安全科学与工程
- 5 篇 土木工程
- 4 篇 生物工程
- 3 篇 生物医学工程（可授...
- 2 篇 力学（可授工学、理...
- 2 篇 仪器科学与技术
- 2 篇 化学工程与技术
113 篇 理学
- 68 篇 数学
- 46 篇 系统科学
- 11 篇 物理学
- 8 篇 统计学（可授理学、...
- 4 篇 生物学
67 篇 管理学
- 56 篇 管理科学与工程(可...
- 20 篇 工商管理
- 12 篇 图书情报与档案管...
10 篇 法学
- 6 篇 社会学
- 4 篇 法学
7 篇 艺术学
- 7 篇 设计学（可授艺术学...
5 篇 经济学
- 5 篇 应用经济学
1 篇 医学

主题

207 篇 hardware
113 篇 computer archite...
94 篇 embedded system
67 篇 application soft...
60 篇 embedded systems
60 篇 permission
55 篇 system-on-a-chip
51 篇 computational mo...
48 篇 field programmab...
47 篇 algorithm design...
47 篇 software
41 篇 energy consumpti...
40 篇 costs
37 篇 system-on-chip
34 篇 real time system...
34 篇 space exploratio...
34 篇 embedded softwar...
32 篇 timing
32 篇 high level synth...
31 篇 system-level des...

机构

8 篇 center for embed...
8 篇 department of el...
7 篇 univ calif river...
7 篇 department of co...
6 篇 school of comput...
6 篇 arizona state un...
6 篇 center for embed...
6 篇 institute for in...
5 篇 princeton univ d...
5 篇 school of inform...
5 篇 philips research...
5 篇 university of er...
5 篇 nec laboratories...
4 篇 natl taiwan univ...
4 篇 department of co...
4 篇 politecn torino ...
4 篇 carnegie mellon ...
4 篇 tu braunschweig
4 篇 university of ca...
4 篇 university of do...

作者

9 篇 sri parameswaran
9 篇 ogras umit y.
9 篇 nikil dutt
8 篇 leupers rainer
7 篇 rolf ernst
7 篇 teich juergen
7 篇 robert p. dick
7 篇 parameswaran sri
6 篇 jiang wei
6 篇 dick robert p.
6 篇 dutt nikil
6 篇 mitra tulika
6 篇 rainer leupers
6 篇 andreas gerstlau...
6 篇 jha niraj k.
5 篇 pasricha sudeep
5 篇 gerd ascheid
5 篇 greg stitt
5 篇 jinyu zhan
5 篇 ernst rolf

语言

1,034 篇 英文
1 篇 其他

检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

共 1035 条记录，以下是421-430 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Formal modelling and transformations of processor instruction sets

Formal modelling and transformations of processor instructio...

引用

acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Andrey Mokhov Danil Sokolov Maxim Rykunov Alex Yakovlev University of Newcastle UK

Instruction sets of modern processors contain hundreds of instructions defined on a relatively small set of datapath components and distinguished by their codes and the order in which they activate these components. Optimal design of an instruction set for a particular combination of available hardware components and software requirements is crucial for system performance and is a challenging task involving a lot of heuristics and high-level design decisions. The overall design process is significantly complicated by inefficient representation of instructions, which are usually described individually despite the fact that they share a lot of common behavioural patterns. This paper presents a new methodology for compact graph representation of processor instruction sets, which gives the designer a new high-level perspective for reasoning on large sets of instructions without having to look at each of them individually. This opens the way for various transformation and optimisation procedures, which are formally defined and explained on several examples, as well as practically evaluated on an FPGA platform.

关键词： Instruction sets hardware Registers Microprocessors Mathematical model Complexity theory

来源：评论

学校读者我要写书评

暂无评论

Proprietary code to non-proprietary benchmarks: synthesis techniques for scalable benchmarks 11

Proprietary code to non-proprietary benchmarks: synthesis te...

引用

Proceedings of the 2nd acm/SPEC international conference on Performance engineering

作者： Lizy Kurian John The University of Texas at Austin Austin TX USA

ISBN: (纸本)9781450305198

Real world applications constitute intellectual property and simultaneous design of hardware and software is made very difficult due to the need for disclosing proprietary software to hardware designers. Consider a smart phone for which applications are developed by various third parties or a military system, where the classified applications are developed in-house at the military while hardware is procured from standard vendors. Design of hardware that gives good performance and low power can be done if hardware designers had access to the software, so they can understand the features of the software and tune various hardware features to the software characteristics. While non-disclosure agreements and legal arrangements can be used to partly solve the problem, it will be much more convenient to have a mechanism to create proxies of proprietary benchmarks that have the performance (and power) characteristics of the source, but not the *** our past research, we created a benchmark synthesis process for early design exploration. The benchmark synthesis process consists of constructing a proxy workload that possesses approximately the same performance and power characteristics as the original workload [1-3]. The synthesis comprises of two steps: (1) profiling the real-world proprietary workload to measure its inherent behavior characteristics, and (2) modeling the measured workload attributes into a synthetic benchmark program. The set of workload characteristics can be thought of as a signature that uniquely describes the workload's inherent behavior, independent of the microarchitecture. The cloned code in fact has no functionality and cannot be reverse engineered to create the original code or algorithms. The cloned software can be freely released to hardware developers so that they can optimize the hardware they deliver to their clients to yield improved *** talk will describe the benchmark synthesis process as well as the status of the r

关键词： synthetic benchmarks computer design workload synthesis

来源：评论

学校读者我要写书评

暂无评论

hardware/software co-design for high performance computing: Challenges and opportunities 10

Hardware/software co-design for high performance computing: ...

引用

Proceedings of the eighth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Hu, X. Sharon Murphy, Richard C. Dosanjh, Sudip Olukotun, Kunle Poole, Stephen Department of Computer Science and Engineering University of Notre Dame Notre Dame IN United States Scalable Computer Architecture Department Sandia National Laboratories Albuquerque NM United States Computer and Software Systems Department Sandia National Laboratories Albuquerque NM United States Department of Electrical Engineering Stanford University Stanford CA United States Computational Sciences Division Oak Ridge National Lab Oak Ridge TN United States

ISBN: (纸本)9781605589053

This special session aims to introduce to the hardware/software codesign community challenges and opportunities in designing high performance computing (HPC) systems. Though embedded system design and HPC system design have traditionally been considered as two separate areas of research, they in fact share quite some common features, especially as CMOS devices continue along their scaling trends and the HPC community hits hard power and energy limits. Understanding the similarities and differences between the design practices adopted in the two areas will help bridge the two communities and lead to design tool developments benefiting both communities.

关键词： hardware-software codesign

来源：评论

学校读者我要写书评

暂无评论

parSC: Synchronous parallel systemC simulation on multi-core host architectures 10

parSC: Synchronous parallel SystemC simulation on multi-core...

引用

Proceedings of the eighth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Schumacher, Christoph Leupers, Rainer Petras, Dietmar Hoffmann, Andreas Institute for Integrated Signal Processing Systems RWTH Aachen University Germany Synopsys Inc. Aachen Germany

ISBN: (纸本)9781605589053

Time-consuming cycle-accurate MPSoC simulation is often needed for debugging and verification. Its practicability is put at risk by the growing MPSoC complexity. This work presents a conservative synchronous parallel simulation approach along with a systemC framework to accelerate tightly-coupled MPSoC simulations on multi-core hosts. Key contribution is the implementation strategy, which utilizes techniques from the high-performance computing domain. Results show speed-ups of up to 4.4 on four host cores.

关键词： system-on-chip

来源：评论

学校读者我要写书评

暂无评论

hardware/software optimization of error detection implementation for real-time embedded systems 10

Hardware/software optimization of error detection implementa...

引用

Proceedings of the eighth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Lifa, Adrian Eles, Petru Peng, Zebo Izosimov, Viacheslav Linköping University Linköping Sweden Embedded Intelligent Solutions Linköping Sweden

ISBN: (纸本)9781605589053

This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safety-critical applications. An application is modeled as a set of processes communicating by messages. Processes are mapped on computation nodes connected to the communication infrastructure. To provide resiliency against transient faults, efficient error detection and recovery techniques have to be employed. Our main focus in this paper is on the efficient implementation of the error detection mechanisms. We have developed techniques to optimize the hardware/software implementation of error detection, in order to minimize the global worst-case schedule length, while meeting the imposed hardware cost constraints and tolerating multiple transient faults. We present two design optimization algorithms which are able to find feasible solutions given a limited amount of resources: the first one assumes that, when implemented in hardware, error detection is deployed on static reconfigurable FPGAs, while the second one considers partial dynamic reconfiguration capabilities of the FPGAs.

关键词： Error detection

来源：评论

学校读者我要写书评

暂无评论

Statistical approach in a system level methodology to deal with process variation 10

Statistical approach in a system level methodology to deal w...

引用

Proceedings of the eighth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Sanz Pineda, Concepción Prieto, Manuel Gómez, José Ignacio Tenllado, Christian Catthoor, Francky Dpto. de Arquitectura de Computadores Y Automática Universidad Complutense de Madrid Madrid 28040 Spain Inter-University Microelectronics Center IMEC Leuven 3001 Belgium

ISBN: (纸本)9781605589053

The impact of process variation in state of the art technology makes traditional (worst case) designs unnecessarily pessimistic, which translates to suboptimal designs in terms of both energy consumption and performance. In this context, developing variation aware design methodologies becomes a must. These techniques should provide better performance-energy balances while the percentage of faulty products keeps controlled. Furthermore, it would be advisable to consider adaptations of the system during lifetime, in order to provide robustness against ageing. In this paper we propose a design approach which tackles process variation on the memory system by using multimode memories. At design time we perform a heuristic exploration using probabilistic models of these memories, which generates a set of system configurations that minimize energy consumption for a given set of timing constraints. The percentage of systems that will satisfy these deadlines, even under process variation, is taken as a design parameter. Additionally, if system monitors are available, a setup stage optimizes the initial set of configurations for the actual memory parameters. Our simulations show that this methodology provides significant energy savings while still meeting timing constraints. © 2010 acm.

关键词： Energy utilization

来源：评论

学校读者我要写书评

暂无评论

An elastic software Cache with fast prefetching for motion compensation in video decoding 10

An elastic software Cache with fast prefetching for motion c...

引用

Proceedings of the eighth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Chao, Ping Lin, Youn-Long Department of Computer Science National Tsing Hua University Hsin-Chu 30013 Taiwan

ISBN: (纸本)9781605589053

Real-time decoding of ultrahigh resolution video using multicore architectures is important for future embedded systems. However, memory bandwidth is still a bottleneck of system performance. Video coding performs irregular DRAM access resulting in very low and unstable efficiency. The conventional cache approach is insufficient because it reduces only the redundant accesses to data that has already been fetched during prior-macroblock decoding. We present an Elastic software Cache (ESC) for ultrahigh resolution video decoding on Scratchpad Memory (SPM)-based systems. Utilizing access region analysis, our latency-optimized prefetching scheme rearranges accesses to minimize both data redundancy and DRAM access latency. Compared to the conventional cache approach, our scheme requires only 4.6 Kbytes of SPM space but it can save up to 25% of memory access cycles resulting in both higher performance and lower power.

关键词： Decoding

来源：评论

学校读者我要写书评

暂无评论

Towards a synthesis semantics for systemC channels 10

Towards a synthesis semantics for SystemC channels

引用

Proceedings of the eighth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Grüttner, Kim Kleen, Henning Oppenheimer, Frank Rettberg, Achim Nebel, Wolfgang OFFIS Institute for Information Technology Escherweg 2 26121 Oldenburg Germany Department of Computer Science Faculty II Carl von Ossietzky University Oldenburg Ammerländer Heerstrasse 114-118 26111 Oldenburg Germany

ISBN: (纸本)9781605589053

In this paper we propose a synthesis semantics for systemC™ channels, which contribute to a clear separation between computation (algorithm) and communication, whereas communication related parts are modelled through either primitive or hierarchical channels. We present a synthesisable replacement for systemC primitive channels that allows deterministic access scheduling and user-constrained refinement for HW/HW and HW/SW communication. We demonstrate the feasibility of our approach through synthesis and exploration of a communication intensive packet switch design under consideration of different configurations and communication refinements.

关键词： Semantics

来源：评论

学校读者我要写书评

暂无评论

Improving platform-based system synthesis by satisfiability Modulo theories solving 10

Improving platform-based system synthesis by satisfiability ...

引用

Proceedings of the eighth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Reimann, Felix Glab, Michael Haubelt, Christian Eberl, Michael Teich, Jürgen University of Erlangen Nuremberg Germany

ISBN: (纸本)9781605589053

Due to the ever increasing system complexity, deciding whether a given platform is sufficient to implement a set of applications under given constraints becomes a serious bottleneck in platform-based design. As a remedy, the work at hand proposes a novel automatic platform-based system synthesis procedure, inspired by techniques developed in the context of automatic system verification known as Satisfiability Modulo Theories. It tightly couples the computation of a feasible allocation and binding with nonfunctional constraint checking where, in contrast to existing approaches, not only linear constraints but even nonlinear constraints are supported. This allows to efficiently prove whether there exists a feasible implementation of a set of applications on the given platform with respect to both, functional and nonfunctional constraints. Moreover, an approach for early learning based on feasibility checking of partial implementations is proposed that can signifiantly improve the synthesis runtime, especially in case the selected platform imposes stringent constraints on the implementation. The effectiveness of this approach is shown for an automotive ECU network design that requires Modular Performance Analysis to ensure non-functional nonlinear timing constraints.

关键词： Formal logic

来源：评论

学校读者我要写书评

暂无评论

An introduction to the systemC synthesis subset standard 10

An introduction to the SystemC synthesis subset standard

引用

Proceedings of the eighth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Coussy, Philippe Takach, Andres McNamara, Michael Meredith, Mike Université de Bretagne-Sud Rue de Saint Maude Lorient Cedex 56321 France Mentor Graphics 8005 SW Boeckman Rd. Wilsonville OR 97070 United States Cadence 2655 Seely Avenue San Jose CA 95134 United States Forte Design Systems 16150 NE 85th Street Redmond WA 98052 United States

ISBN: (纸本)9781605589053

High-level synthesis (HLS) offers the prospect of improving the productivity digital system design and the quality of the resulting implementations. Designing at higher levels of abstraction is a natural way for coping with system design complexity, for verifying earlier in the design process and for increasing design reuse [1][2][7]. OSCI's synthesis working group (SWG) [3] has led the effort of defining the synthesis subset for systemC that is suitable for HLS. Draft version 1.3 [4] of the document was released for public review in August 2009. While still in draft form, the released document provides guidance to both tool providers and users on the subset that is being proposed and the ability to provide feedback to the SWG on the draft. This tutorial will provide a brief introduction and three case studies on the use of HLS and the current systemC synthesis subset draft for hardware design of digital systems.

关键词： High level synthesis

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共104页 << < 39 40 41 42 43 44 45 46 47 48 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：