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Proceedings of the eighth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Li, Hao Tong, Dong Huang, Kan Cheng, Xu Microprocessor Research and Development Center Peking University Beijing China

ISBN: (纸本)9781605589053

Full-system emulation on FPGA(Field-Programmable Gate Array) with real-world workloads can enhance the confidence of SoC(system-on-Chip) design. However, since FPGA emulation requires complete implementation of key modules and provides weak visibility, it is time-consuming. This paper proposes FEMU, a hybrid firmware/hardware emulation framework for SoC verification. The core of FEMU is implemented by transplanting QEMU, a full-system emulator, from OS level to BIOS level, so we can directly emulate devices upon hardware. Moreover, FEMU provides programming interfaces to simplify device modeling in firmware. Based on an auxiliary set of hardware modules, FEMU allows hybrid full-system emulation with the combination of real hardware and emulated firmware model. Therefore, FEMU can facilitate full-system emulation in three aspects. First, FEMU enables full-system emulation with the minimum hardware implementation, so the DUT (Design Under Test) module can be verified under target application as early as possible. Second, by comparing the execution traces generated using real hardware and emulated firmware model, respectively, FEMU helps locate and fix bugs occurred in the full-system emulation. Third, by replacing un-verified hardware modules with emulated firmware models, FEMU helps isolating design issues in multiple modules. In a practical SoC project, FEMU helped us identify several design issues in full-system emulation. In addition, the evaluation results show that the emulation speed of FEMU is comparable with QEMU after transplantation.

关键词： system-on-chip

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A holistic approach to network-on-chip synthesis 10

A holistic approach to network-on-chip synthesis

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Proceedings of the eighth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Leary, Glenn Chatha, Karam S. Department of CSE Arizona State University P.O. Box 875406 Tempe AZ 85287-5406 United States

ISBN: (纸本)9781605589053

Application specific Network-on-Chip (NoC) architectures have emerged as a leading technology to address the communication woes of multi-processor system-on-Chip architectures. synthesis approaches for custom NoC must address several requirements including cumulative bandwidth and transaction level (TL) communication requirements, multiple application use-cases, deadlock avoidance, and router port bandwidth and arity constraints. In this paper we present a holistic algorithm for NoC synthesis which is able to address all these requirements together in an integrated manner. The approach is able to generate designs that consume minimum dynamic power consumption, and at most twice the number of routers (and leakage power) as an optimal solution. In terms of performance the technique is able to generate NoC designs with very low average communication latencies (verified by actual simulations) and equally low standard deviation (jitter) while utilizing simple best effort routers. We evaluated the effectiveness and quality of the proposed technique by comparisons with two existing approaches. Extensive experimental results are presented for synthetic/realistic multiple use case applications, cumulative/transaction traffic requirements, increasing application bandwidth requirements, and different port arity constraints.

关键词： Network-on-chip

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Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming 10

Automatic parallelization of embedded software using hierarc...

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Proceedings of the eighth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Cordes, Daniel Marwedel, Peter Mallik, Arindam Informatik Centrum Dortmund Joseph-von-Fraunhofer-Str. 20 Dortmund Germany Imec Belgium Kapeldreef 75 Leuven Belgium

ISBN: (纸本)9781605589053

The last years have shown that there is no way to disregard the advantages provided by multiprocessor system-on-Chip (MPSoC) architectures in the embedded systems domain. Using multiple cores in a single system enables to close the gap between energy consumption, problems concerning heat dissipation, and computational power. Nevertheless, these benefits do not come for free. New challenges arise, if existing applications have to be ported to these multiprocessor platforms. One of the most ambitious tasks is to extract efficient parallelism from these existing sequential applications. Hence, many parallelization tools have been developed, most of them are extracting as much parallelism as possible, which is in general not the best choice for embedded systems with their limitations in hardware and software support. In contrast to previous approaches, we present a new automatic parallelization tool, tailored to the particular requirements of the resource constrained embedded systems. Therefore, this paper presents an algorithm which automatically steers the granularity of the generated tasks, with respect to architectural requirements and the overall execution time reduction. For this purpose, we exploit hierarchical task graphs to simplify a new integer linear programming based approach in order to split up sequential programs in an efficient way. Results on real-life benchmarks have shown that the presented approach is able to speed sequential applications up by a factor of up to 3.7 on a four core MPSoC architecture.

关键词： Embedded systems

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system-level reliability modeling for MPSoCs 10

System-level reliability modeling for MPSoCs

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Proceedings of the eighth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Xiang, Yun Chantem, Thidapat Dick, Robert P. Hu, X. Sharon Shang, Li EECS Department University of Michigan Ann Arbor MI 48109 United States CSE Department University of Notre Dame Notre Dame IN 46556 United States ECE Department University of Colorado Boulder CO 80309 United States

ISBN: (纸本)9781605589053

The reliability of multi-processor systems-on-chip (MPSoCs) is affected by several inter-dependent system-level and physical effects. Accurate and fast reliability modeling is a primary challenge in the design and optimization of reliable MPSoCs. This paper presents a reliability modeling framework that integrates device-, component-, and system-level models. This framework contains modules for electromigration, time-dependent dielectric breakdown, stress migration, and variable-amplitude thermal cycling. A new statistical reliability distribution is proposed for accurate characterization of components containing too few devices for an extreme value distribution to be appropriate. A hierarchical system-level survival lattice based Monte Carlo technique is used to estimate the temporal fault distributions of MPSoCs that use arbitrary static and dynamic reliability-enhancing redundancy schemes. Physical process variation, which may have a significant impact on MPSoC reliability, is considered in the model. The proposed modeling technique has 5% average error in mean time to failure and reduces simulation time by nearly 3 orders of magnitude relative to a non-hierarchical Monte Carlo technique.

关键词： Hierarchical systems

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FastFwd: An efficient hardware acceleration technique for trace-driven network-on-chip simulation 10

FastFwd: An efficient hardware acceleration technique for tr...

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Proceedings of the eighth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Krishnaiah, Gummidipudi Silpa, B.V.N. Panda, Preeti Ranjan Kumar, Anshul Dept. of CSE IIT Delhi New Delhi India

ISBN: (纸本)9781605589053

We present an efficient emulation-based technique to accelerate architecture exploration of networks-on-chip (NoCs). The large design space of NoC along with its growing complexity that results in low simulation speeds on host machines have motivated the need for hardware accelerators for speeding up the simulation. For example, simulation of applications with real life problem sizes could take weeks on a host machine. FPGA acceleration is a promising strategy for speeding up NoC simulations by several orders of magnitude. However, it is required to simulate a few billion network transactions of the application during NoC exploration, and this could still take tens of minutes even with an FPGA-based emulator. With the increasing complexity of architectures and applications, reducing emulation time is a key concern. We propose a technique, FastFwd, to minimize emulation time by efficiently identifying and eliminating redundant cycles during a trace-based NoC simulation. We have studied the implications of the additional FPGA hardware required for implementing our technique. A naïve implementation could lead to poor scalability and increase the required DRAM bandwidth, both of which ultimately impact the emulation speed negatively. We propose a hierarchical controller architecture to resolve the scalability issue, and a compressed representation of traces for mitigating the increased DRAM bandwidth requirement. Our experiments with several benchmarks have shown that the FPGA emulation with our technique reduces the average emulation time by a factor of 2 when compared to a conventional emulation.

关键词： Network-on-chip

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Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications 10

Optimal synthesis of latency and throughput constrained pipe...

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Proceedings of the eighth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Javaid, Haris He, Xin Ignjatovic, Aleksander Parameswaran, Sri School of Computer Science and Engineering University of New South Wales Sydney Australia

ISBN: (纸本)9781605589053

A streaming application, characterized by a kernel that can be broken down into independent tasks which can be executed in a pipelined fashion, inherently allows its implementation on a pipeline of Application Specific Instruction set Processors (ASIPs), called a pipelined MPSoC. The latency and throughput requirements of streaming applications put constraints on the design of such a pipelined MPSoC, where each ASIP has a number of available configurations differing by additional instructions, and instruction and data cache sizes. Thus, the design space of a pipelined MPSoC is all the possible combinations of ASIP configurations (design points). In this paper, a methodology is proposed to optimize the area of a pipelined MPSoC under a latency or a throughput constraint. The final design point is a set of ASIP configurations with one configuration for each ASIP. We proposed an Integer Linear Programming (ILP) based solution to the area optimization problem under a latency constraint, and an algorithm for optimization of pipelined MPSoC area under a throughput constraint. The proposed solutions were evaluated using four streaming applications: JPEG encoder;JPEG decoder;MP3 encoder;and H.264 decoder. The time to find the Pareto front of each pipelined MPSoC was less than 4 minutes where design spaces had up to 1016 design points, illustrating the applicability of our approach.

关键词： Throughput

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hardware/software co-design for high performance computing: Challenges and opportunities

Hardware/software co-design for high performance computing: ...

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作者： Hu, X. Sharon Murphy, Richard C. Dosanjh, Sudip Olukotun, Kunle Poole, Stephen Department of Computer Science and Engineering University of Notre Dame Notre Dame IN United States Scalable Computer Architecture Department Sandia National Laboratories Albuquerque NM United States Computer and Software Systems Department Sandia National Laboratories Albuquerque NM United States Department of Electrical Engineering Stanford University Stanford CA United States Computational Sciences Division Oak Ridge National Lab. Oak Ridge TN United States

ISBN: (纸本)9781605589053

This special session aims to introduce to the hardware/software codesign community challenges and opportunities in designing high performance computing (HPC) systems. Though embedded system design and HPC system design have traditionally been considered as two separate areas of research, they in fact share quite some common features, especially as CMOS devices continue along their scaling trends and the HPC community hits hard power and energy limits. Understanding the similarities and differences between the design practices adopted in the two areas will help bridge the two communities and lead to design tool developments benefiting both communities. © 2010 acm.

关键词： hardware-software codesign

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From ESL 2010 to ESL 2015 10

From ESL 2010 to ESL 2015

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Proceedings of the eighth IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Jeremiassen, Tor Martin, Grant Kogel, Tim Donlin, Adam Takach, Andres Chatha, Karam Texas Instruments United States Tensilica United States Synopsys United States Xilinx United States Mentor Graphics United States Arizona State University United States

ISBN: (纸本)9781605589053

In 2010, a wave of consolidation swept over the Electronic system Level (ESL) design industry. It brought ESL providers together with mainstream EDA houses and created opportunities for new ESL ventures. This paper contains short summaries of presentations in a special session focusing on the future of ESL. The session has two goals: the first is to present the state of the art in ESL tools and practice and, second, share a vision of the technical challenges that the next generation of ESL companies should address. The session includes a mix of perspectives from both ESL solution vendors and end-users and touches all all four ESL use cases: software virtual platforms, performance analysis, high level synthesis and verification.

关键词： High level synthesis

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An introduction to the systemC synthesis subset standard

An introduction to the SystemC synthesis subset standard

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作者： Coussy, Philippe Takach, Andres McNamara, Michael Meredith, Mike Université de Bretagne-Sud Rue de Saint Maude Lorient Cedex 56321 France Mentor Graphics 8005 SW Boeckman Rd. Wilsonville OR 97070 United States Cadence 2655 Seely Avenue San Jose CA 95134 United States Forte Design Systems 16150 NE 85th Street Redmond WA 98052 United States

ISBN: (纸本)9781605589053

High-level synthesis (HLS) offers the prospect of improving the productivity digital system design and the quality of the resulting implementations. Designing at higher levels of abstraction is a natural way for coping with system design complexity, for verifying earlier in the design process and for increasing design reuse [1][2][7]. © 2010 acm.

关键词： High level synthesis

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High-Level Design and Validation of the BlueSPARC Multithreaded Processor

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND systemS 2010年第10期29卷 1459-1470页

作者： Chung, Eric S. Hoe, James C. Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA

This paper presents our experiences in using high-level methods to design and validate a 16-way multithreaded microprocessor called BlueSPARC. BlueSPARC is an in-order, high-throughput processor supporting complex features such as privileged-mode operations, memory management, and a nonblocking cache subsystem. Using a high-level design language called Bluespec system Verilog (BSV), our final implementation achieves comparable synthesis quality to a similar commercial microprocessor developed using conventional register transfer level flows, and is capable of running unmodified commercial applications while hosted on a Xilinx XCV2P70 field-programmable gate array (FPGA) at 90 MHz. To validate our implementation, an FPGA-accelerated approach was developed to efficiently check the correct execution of real, nondeterministic multithreaded programs running on the BlueSPARC processor. Together, the high-level language features of BSV along with our validation approach enabled us to achieve a working FPGA-based implementation in less than one man-year.

关键词： hardware description language (HDL) microprocessor synthesis validation

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