This paper presents an investigation into the possibility of using a regular concurrent programming language for modeling and implementing digital circuits. Some of the reasons for using an existing language include t...
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This paper presents an investigation into the possibility of using a regular concurrent programming language for modeling and implementing digital circuits. Some of the reasons for using an existing language include the ability to use existing compilers and analysis tools for circuit design and verification. Another important reason is the ever increasing need to model complete systems that comprise interacting software and hardware in a single framework which facilitates easier migration of sub-components between hardware and software implementations compared to multi-model approaches. To this end we present the design of the Kiwi system which models digital circuits with concurrent programs using a standard library in C# for multi-threaded programming. Kiwi models can be executed using a regular C# compiler. Also, the compiled bytecode can be automatically converted into circuits using our Kiwi hardwaresynthesissystem.
We present an efficient emulation-based technique to accelerate architecture exploration of networks-on-chip (NoCs). The large design space of NoC along with its growing complexity that results in low simulation speed...
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The reliability of multi-processor systems-on-chip (MPSoCs) is affected by several inter-dependent system-level and physical effects. Accurate and fast reliability modeling is a primary challenge in the design and opt...
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A streaming application, characterized by a kernel that can be broken down into independent tasks which can be executed in a pipelined fashion, inherently allows its implementation on a pipeline of Application Specifi...
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We implemented a hardware accelerated system for deep packet inspection. The proposed system makes use of operation level and connection level parallelism to achieve a maximum processing rate of 595.2Mb/s. The system ...
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We implemented a hardware accelerated system for deep packet inspection. The proposed system makes use of operation level and connection level parallelism to achieve a maximum processing rate of 595.2Mb/s. The system supports 25 mandatory patterns running at 125 MHz on a Xilinx Virtex 5 FPGA.
Power profiling methods are indispensible in the power-aware design of HW/SW systems. By extending functional emulators with power estimation hardware, high-level power information can be derived during run-time, yiel...
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Power profiling methods are indispensible in the power-aware design of HW/SW systems. By extending functional emulators with power estimation hardware, high-level power information can be derived during run-time, yielding a considerable speed-up as compared to simulation based approaches. A key enabler for the widespread use of the power emulation methodology is the automation of both power model creation and HDL adaptation. In this paper, we outline our system-level power emulation technique as well as its automatic power modeling and hardware adaptation. Furthermore, applications in the field of HW/SW power management are illustrated.
This paper describes the architecture of a high-speed regular expression matching system implemented by the [Ii][Ss][Uu][0-2]{4} team from Iowa State University for the 2010 MEMOCODE competition. The purpose of this s...
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This paper describes the architecture of a high-speed regular expression matching system implemented by the [Ii][Ss][Uu][0-2]{4} team from Iowa State University for the 2010 MEMOCODE competition. The purpose of this system is to detect malicious patterns in high-speed network data streams. The core functionality is implemented on a Stratix III 260 FPGA, and software running on a Xeon processor is used to transfer data to/from main memory and the FPGA. An interesting aspect of this architecture is the novel use of context switching resources to avoid buffering packets of connections whose classification are pending. The implemented solution detects malicious patterns at over 500 Mbps, and is estimated to scale to support well over 400 rules on our Stratix III FPGA.
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