The proceedings contain 50 papers. The topics discussed include: a compositional modelling framework for exploring MPSoC systems;a high-level virtual platform for early MPSoC software development;on compile-time evalu...
ISBN:
(纸本)9781605586281
The proceedings contain 50 papers. The topics discussed include: a compositional modelling framework for exploring MPSoC systems;a high-level virtual platform for early MPSoC software development;on compile-time evaluation of process partitioning transformations for kahn process networks;SARA: StreAm register allocation;dynamically utilizing computation accelerators for extensible processors in a software approach;scalable and retargetable simulation techniques for multiprocessor systems;an on-chip interconnect and protocol stack for multiple communication paradigms and programming models;a monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures;a DP-network for optimal dynamic routing in network-on-chip;LOP: a novel SRAM-based architecture for low power and high throughput packet classification;memory-efficient distribution of regular expressions for fast deep packet inspection;and on-the-fly hardware acceleration for protocol stack processing in next generation mobile devices.
Electronic system Level (ESL) design manages the enormous complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-the-art for describing complex communicatio...
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Electronic system Level (ESL) design manages the enormous complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-the-art for describing complex communication without all the details. As ESL language, systemC has become the de facto standard. Since the systemC TLM models are used for early software development and as reference for hardware implementation their correct functional behavior is crucial. Admittedly, the best possible verification quality can be achieved with formal approaches. However, formal verification of TLM models is a hard task. Existing methods basically consider local properties or have extremely high run-time. In contrast, the approach proposed in this paper can verify “true” TLM properties, i.e. major TLM behavior like for instance the effect of a transaction and that the transaction is only started after a certain event can be proven. Our approach works as follows: After a fully automatic systemC-to-C transformation, the TLM property is mapped to monitoring logic using C assertions and finite state machines. To detect a violation of the property the approach uses a BMC-based formulation over the outermost loop of the systemC scheduler. In addition, we improve this verification method significantly by employing induction on the C model forming a complete and efficient approach. As shown by experiments state-of-the-art proof techniques allow proving important non-trivial behavior of systemC TLM designs.
We present the inter-task communication technique incorporating the RHSCC (Real-time hardware-software Communcation Channel) that makes it possible to resolve the hardware-software co-design issue of implementing netw...
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Performance estimation of Multi-Processor system-On-Chip (MPSoC) at a high abstraction level is required in order to perform early architecture exploration and accurate design validations. Although abstract executable...
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ISBN:
(纸本)9781605586281
Performance estimation of Multi-Processor system-On-Chip (MPSoC) at a high abstraction level is required in order to perform early architecture exploration and accurate design validations. Although abstract executable models provide interesting functional validation capabilities, they quickly become unsuitable when timing becomes an issue - Native software simulation, a good candidate from the speed point of view, suffers from this issue. In this paper, we present a transactional level simulation environment that allows reliable performance estimation with a specific focus on software timing estimation on multi processor architectures. The embedded software is compiled natively on the host running the simulation and instrumented to reflect its execution on a specific target processor and then executed on a simulation model of the underlying hardware. The key contribution of this work is the use of both static and dynamic analysis, that allow realistic timing measurements in native software simulation. Experimental results show the efficiency of the proposed method to accurately estimate software performance in co-simulation environments. Copyright 2009 acm.
Multiprocessor system-on-Chips (MPSoCs) are nowadays widely used, but the problem of their software development persists to be one of the biggest challenges for developers. Virtual Platforms (VPs) are introduced to th...
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ISBN:
(纸本)9781605586281
Multiprocessor system-on-Chips (MPSoCs) are nowadays widely used, but the problem of their software development persists to be one of the biggest challenges for developers. Virtual Platforms (VPs) are introduced to the industry, which allow MPSoC software development without a hardware prototype. Nevertheless, for developers in early design stage where no VP is available, the software programming support is not satisfactory. This paper introduces a High-level Virtual Platform (HVP) which aims at early MPSoC software development. The framework provides a set of tools for abstract MPSoC simulation and the corresponding application programming support in order to enable the development of reusable C code at a high level. The case study performed on several MPSoCs shows that the code developed on the HVP can be easily reused on different target platforms. Moreover, the high simulation speed achieved by the HVP also improves the design efficiency of software developers. Copyright 2009 acm.
In this paper, a novel approach for integrating time slice based resource access in global performance analysis of distributed real-time critical embedded systems is presented. The performance analysis approach itself...
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ISBN:
(纸本)9781605586281
In this paper, a novel approach for integrating time slice based resource access in global performance analysis of distributed real-time critical embedded systems is presented. The performance analysis approach itself is based on bottom-up analysis of communicating processes under consideration of synchronization by inter-process communication and complex internal control flows of the processes. This general analysis methodology is extended concerning concurrent occupation of shared resources using time slice based access methods. The defined extensions are parameterizable for describing arbitrary communication media access schedules and software schedules on shared computation resources, although the explicit focus in this paper is on software scheduling. The applicability of the analysis extensions is presented by a case study of a multimedia subsystem implemented in systemC. Copyright 2009 acm.
In recent years, it is increasingly common to see using application specific instruction set processors (ASIPs) in embedded system designs. These ASIPs can offer the ability of customizing hardware computation acceler...
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ISBN:
(纸本)9781605586281
In recent years, it is increasingly common to see using application specific instruction set processors (ASIPs) in embedded system designs. These ASIPs can offer the ability of customizing hardware computation accelerators for an application domain. Along with instruction set extensions (ISEs), the customized accelerators can significantly improve the performance of embedded processors, which has already been exemplified in previous research work and industrial products. However, these accelerators in ASIPs can only accelerate the applications that are compiled with ISEs. Those applications compiled without ISEs can not benefit from the hardware accelerators at all. In this paper, we propose using software dynamic binary translation to overcome this problem, i.e. dynamically utilizing the accelerators. Unlike a static approach, dynamically utilizing accelerator poses many new problems. This paper comprehensively explores the techniques and design choices for solving these problems, and demonstrates the effectiveness by the results of experiments. Copyright 2009 acm.
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