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A compositional modelling framework for exploring MPSoC systems 09

A compositional modelling framework for exploring MPSoC syst...

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Embedded systems Week 2009, ESWEEK 2009 - 7th IEEE/acm international conference on hardware/software-Co-Design and system synthesis, CODES+ISSS 2009

作者： Tranberg-Hansen, Anders Sejer Madsen, Jan Technical University of Denmark Kgs. Lyngby Denmark

ISBN: (纸本)9781605586281

This paper presents a novel compositional framework for system level performance estimation and exploration of Multi-Processor system On Chip (MPSoC) based systems. The main contributions are the definition of a compositional model which allows quantitative performance estimation to be carried out throughout all design phases ranging from early functional specification to actual cycle accurate and bit true descriptions of the system. This is possible, because a seamless refinement of models is supported by allowing the existence of models described at multiple levels of abstraction to co-exist and communicate. In order to illustrate the use of the framework, a mobile digital audio processing platform, supplied by the company Bang & Olufsen ICEpower a/s, is considered. Copyright 2009 acm.

关键词： system-on-chip

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A HW/SW Co-design Methodology: An Accurate Power Efficiency Model and Design Metrics for Embedded system

A HW/SW Co-design Methodology: An Accurate Power Efficiency ...

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3rd international Workshop on e-Activity (IWEA2009)/10th ACIS international conference on software Engineering Artificial Intelligence, Networking and Parallel/Distributed Computing

作者： Iftikhar, Khan Jeong, Taikyeong Ted Park, Gyungleen Ambler, Anthony P. Myongji Univ Dept Commun Eng Seoul South Korea Jeju Natl Univ Dept Comp Stat Jeju-do South Korea Univ Texas Austin Dept Elect & Comp Eng Austin TX 78712 USA

ISBN: (纸本)9780769536422

Low-power embedded system design has become extremely important in the most recent years. To fulfill system-level design requirements and time-to-market constraints, a power-driven methodology is essential during embedded system design. The aim of this paper is to introduce accurate and efficient power metrics included in a hardware/software (HW/SW) co-design environment to show the system-level partitioning and design. In order to verify the design effectiveness of hardware/software co-design synthesis, we consider the digital power dissipation methodology and its power reduction techniques. To maximize the performance of system, we developed hierarchical design technique and co-design synthesis for power efficient HW/SW co-design process. In the end, we provided simulation results for single circuit with new design vs. circuit integration with hierarchical power efficiency system (HPES), multiple circuits with new design vs. circuit integration with HPES, new design and no load vs. circuit integration with HPES, new design with load vs. circuit integration with HPES.

关键词： Embedded systems hardware/software codesign low-power power metrics

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Building heterogeneous reconfigurable systems with a hardware microkernel 09

Building heterogeneous reconfigurable systems with a hardwar...

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Embedded systems Week 2009, ESWEEK 2009 - 7th IEEE/acm international conference on hardware/software-Co-Design and system synthesis, CODES+ISSS 2009

作者： Agron, Jason Andrews, David Dept. of Computer Science and Computer Engineering University of Arkansas Fayetteville AR United States

ISBN: (纸本)9781605586281

Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a softwarelike productivity for reconfiguring the gates. Unfortunately achieving this promise has been elusive. Modern platform FPGAs are now large enough to support complete heterogeneous Multiprocessor system-On-Chips (MPSoCs), however standardized design flows and programming models for such platforms do not yet exist. To achieve true softwarelike levels of productivity, the design flow and development environment for heterogeneous MPSoCs must resemble that of standard homogeneous systems. In this paper we present a new design flow and run-time system that enables developers to program a heterogeneous MPSoC using standard POSIX-compatible programming abstractions. The ability to use a standard programming model is achieved by using a hardware-based microkernel to provide OS services to all heterogeneous components. This approach makes programming heterogeneous MPSoCs transparent, and can increase programmer productivity by replacing synthesis of custom components with faster compilation of heterogeneous executables. The use of a hardware microkernel provides OS services in an ISA-neutral manner, which allows for seamless synchronization and communication amongst heterogeneous threads. Copyright 2009 acm.

关键词： Field programmable gate arrays (FPGA)

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On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices 09

On-the-fly hardware acceleration for protocol stack processi...

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Embedded systems Week 2009, ESWEEK 2009 - 7th IEEE/acm international conference on hardware/software-Co-Design and system synthesis, CODES+ISSS 2009

作者： Szczesny, David Hessel, Sebastian Bruns, Felix Bilgic, Attila Institute for Integrated Systems Ruhr-Universität Bochum D-44780 Bochum Germany

ISBN: (纸本)9781605586281

In this paper we present a new on-the-fly hardware acceleration approach, based on a smart Direct Memory Access (sDMA) controller, for the layer 2 (L2) downlink protocol stack processing in Long Term Evolution (LTE) and beyond mobile devices. We use virtual prototyping in order to simulate an ARM1176 processor based hardware platform together with the executed software comprising an LTE protocol stack model. The sDMA controller with diff erent hardware accelerator units for the time critical algorithms in the protocol stack is implemented and integrated in the hardware platform. We prove our new hardware/software partitioning concept for the LTE L2 by measuring the average execution time per transport block in the protocol stack at di fferent activated on-the-fly hardware acceleration stages in the sDMA controller. At LTE data rates of 100 Mbit/s, we achieve a speedup of 24% compared to a pure software implementation by enabling the sDMA hardware support for header processing in the protocol stack. Furthermore, an activation of the complete on-the-fly hardware acceleration in the sDMA controller, including on-the-fly deciphering, leads to a speedup of more than 50 %. Finally, at transmission conditions with more computational demands and data rates up to 320 Mbit/s, we obtain acceleration ratios of almost 80 %. Investigations show that our new sDMA on-the-fly hardware acceleration approach in combination with a single-core processor off ers the required computational power for next generation mobile devices. Copyright 2009 acm.

关键词： Embedded systems

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Exploiting data-redundancy in reliability-aware networked embedded system design 09

Exploiting data-redundancy in reliability-aware networked em...

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Embedded systems Week 2009, ESWEEK 2009 - 7th IEEE/acm international conference on hardware/software-Co-Design and system synthesis, CODES+ISSS 2009

作者： Lukasiewycz, Martin Glaß, Michael Teich, Jürgen University of Erlangen-Nuremberg Germany

ISBN: (纸本)9781605586281

This paper presents a system-level design methodology for networked embedded systems that exploits existing data-redundancy to increase their reliability. The presented approach not only supports a reliability-aware embedded system design from scratch, but also enables the redesign of existing systems to increase the reliability with a minimal communication overhead. The proposed approach contributes (a) algorithms to automatically identify inherent data-redundancy and (b) an automatic design space exploration that is capable of exploiting the revealed data-redundancy. A symbolic analysis is presented that quantifies the reliability of a system, enabling the usage of reliability as one of multiple conflicting optimization objectives. The proposed approach is applied to a realworld case study from the automotive area, showing a significantly increased reliability with a negligible communication overhead. Copyright 2009 acm.

关键词： Redundancy

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Using binary translation in event driven simulation for fast and flexible MPSoC simulation 09

Using binary translation in event driven simulation for fast...

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Embedded systems Week 2009, ESWEEK 2009 - 7th IEEE/acm international conference on hardware/software-Co-Design and system synthesis, CODES+ISSS 2009

作者： Gligor, Marius Fournel, Nicolas Pétrot, Frédéric System Level Synthesis Group TIMA Laboratory CNRS/INP Grenoble/UJF 46 avenue Félix Viallet Grenoble France

ISBN: (纸本)9781605586281

In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction level. To have an accurate timing behavior, we had to firstly solve timing issues in processor modeling, secondly define fast and precise cache models, and thirdly solve the synchronization issues due to the different models of computation used in the ISSes and in the rest of the system. We present an integration solution that covers these issues and detail its implementation. We have experimented our proposal using processors models provided by the QEMU framework to replace the existing ISSes and systemC TLM as simulation environment for the whole platform. This approach proposes a range of solutions trading off simulation speed versus accuracy. The experiments show that even for the most precise configuration, the simulation speedup is still significant. Copyright 2009 acm.

关键词： Multiprocessing systems

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Cycle count accurate memory modeling in system level design 09

Cycle count accurate memory modeling in system level design

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Embedded systems Week 2009, ESWEEK 2009 - 7th IEEE/acm international conference on hardware/software-Co-Design and system synthesis, CODES+ISSS 2009

作者： Lo, Yi-Len Li, Mao-Lin Tsay, Ren-Song Logos Advanced System Lab. Dept. of Computer Science National Tsing-Hua University Taiwan

ISBN: (纸本)9781605586281

In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accurate Memory Model (CAMM). Since memory accesses are gradually dominating system activities, a correct and efficient memory timing model is essential to system-level simulation. In general, a CCAMM provides sufficient timing accuracy with low simulation overhead, and hence is preferred over the Simple Fixed Delay Model (SFDM), which has low accuracy, or the CAMM, which has low performance. Our proposed approach can systematically generate the CCAMM and guarantee correctness. The experimental results show that the generated model is as accurate as the Register Transfer Level (RTL) model while running 100X faster. Copyright 2009 acm.

关键词： Computer aided design

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Parallel, hardware-supported interrupt handling in an event-triggered real-time operating system

Parallel, hardware-supported interrupt handling in an event-...

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Embedded systems Week 2009, ESWEEK 2009 - 2009 international conference on Compilers, Architecture, and synthesis for Embedded systems, CASES'09

作者： Scheler, Fabian Hofer, Wanja Oechslein, Benjamin Pfister, Rudi Schröder-Preikschat, Wolfgang Lohmann, Daniel Friedrich-Alexander University Erlangen-Nuremberg Germany

ISBN: (纸本)9781605586267

A common problem in event-triggered real-time systems is caused by low-priority tasks that are implemented as interrupt handlers interrupting and disturbing high-priority tasks that are implemented as threads. This problem is termed rate-monotonic priority inversion, and current software-based solutions are restricted in terms of more sophisticated scheduler features as demanded for instance by the AUTOSAR embedded-operating-system specification. We propose a hardware-based approach that makes use of a coprocessor to eliminate the potential priority inversion. By evaluating a prototypical implementation, we show that our approach both overcomes the restrictions of software approaches and introduces only a slight processing overhead in exchange for increased predictability. Copyright 2009 acm.

关键词： Real time systems

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A tuneable software cache coherence protocol for heterogeneous MPSoCs 09

A tuneable software cache coherence protocol for heterogeneo...

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Embedded systems Week 2009, ESWEEK 2009 - 7th IEEE/acm international conference on hardware/software-Co-Design and system synthesis, CODES+ISSS 2009

作者： Ophelders, Frank Bekooij, Marco J.G. Corporaal, Henk Department of Electrical Engineering Eindhoven University of Technology Netherlands NXP Semiconductors Eindhoven Netherlands Department of EEMCS University of Twente Netherlands

ISBN: (纸本)9781605586281

In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Here, we target at heterogeneous MPSoCs with a network-on-chip (NoC). Existing hardware cache coherence protocols are less suitable for MPSoCs because many off-the-shelf processors used in MPSoCs do not support these protocols. Furthermore, these protocols typically rely on global visibility and serialization of writes which does not match well with the parallel point-to-point communication provided by a NoC. Therefore, we propose a software cache coherence protocol, which can be applied in a heterogeneous MPSoC with a NoC. The software cache coherence protocol relies on explicit synchronization in the software. More specifically, caches are guaranteed to be coherent according to the Release Consistency model, on top of which we have implemented the standard Pthreads communication library. Heterogeneous MPSoCs with off-the-shelf processors can easily be supported, because processors are only required to provide cache control operations, e.g., clean and invalidate. All cache coherence operations are interruptible and do not impact the execution of tasks on other processors, therefore this protocol is suitable for predictable MPSoCs. Our software cache coherence protocol is implemented on an ARM926EJ-S MPSoC which is mapped on an FPGA. From experiments we conclude that the protocol overhead is low for the applications taken from the SPLASH-2 benchmark set. For these applications we observed a speedup between 1.89 and 2.01 on the two processor MPSoC. Copyright 2009 acm.

关键词： Network-on-chip

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A variation-tolerant scheduler for better than worst-case behavioral synthesis 09

A variation-tolerant scheduler for better than worst-case be...

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Embedded systems Week 2009, ESWEEK 2009 - 7th IEEE/acm international conference on hardware/software-Co-Design and system synthesis, CODES+ISSS 2009

作者： Cong, Jason Liu, Albert Liu, Bin Computer Science Department University of California Los Angeles CA United States

ISBN: (纸本)9781605586281

There has been a recent shift in design paradigms, with many turning towards yield-driven approaches to synthesize and design systems. A major cause of this shift is the continual scaling of transistors, making process variation impossible to ignore. Better than worst-case (BTW) designs also exploit these variation effects, while also addressing performance limits due to worst-case analysis. In this paper we first present the variation-tolerant stallable-FSM architecture, which provides fault detection and recovery, allowing circuits to be clocked at better than worst-case delays. Then we propose the BTW scheduler, a 0-1 integer linear programming (ILP) scheduling algorithm with the objective of minimizing the expected latency, to provide a high-level synthesis aid for the stallable-FSM architecture. We implemented the algorithm and ran it through many benchmarks, comparing the results with scheduling algorithms based on worst-case analysis. Our results were promising, showing up to 41% latency reduction for the BTW scheduler, and up to 43% latency reduction when combined with the variation-tolerant architecture. Copyright 2009 acm.

关键词： Scheduling algorithms

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