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CPF: A Cross-Layer Prefetching Framework for High-Density Flash-based Storage

CPF: A Cross-Layer Prefetching Framework for High-Density Fl...

引用

27th Design, Automation and Test in Europe conference and Exhibition (DATE)

作者： Luo, Longfei Wang, Han Yu, Dingcui Lv, Yina Shi, Liang Minist Educ Software Hardware Codesign Engn Res Ctr Shanghai Peoples R China East China Normal Univ Sch Comp Sci & Technol Shanghai Peoples R China City Univ Hong Kong Dept Comp Sci Hong Kong Peoples R China

ISBN: (纸本)9798350348606;9783981926385

The pseudo-single-level-cell (pSLC) technique is widely adopted in high-density flash-based storage to mitigate the performance and endurance problem of high-density flash memory. Furthermore, prefetching schemes can compensate for performance differences among storage tiers. Existing prefetchers are implemented in the operating system (OS) or storage layers. However, OS layer prefetchers are conservative since it is a challenge to achieve both high accuracy and large coverage simultaneously. Storage layer prefetchers are sub-optimal due to the performance differences between pSLC and DRAM. In this paper, a cross-layer prefetching framework (CPF) is proposed to prefetch data selectively. The basic idea is that high-accuracy data will be prefetched to DRAM and large-coverage data will be prefetched to the pSLC flash in storage. To make it practical, an adaptive regulator is further designed to dynamically adjust the cross-layer prefetching to ensure accuracy and coverage. Evaluations show that CPF can improve read performance and reduce data transfer costs significantly.

关键词： Dynamic random access storage

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FPGA-Based hardware/software codesign for Video Encoder on IoT Edge Platforms 23rd

FPGA-Based Hardware/Software Codesign for Video Encoder on...

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23rd international conference on Computational Science and Its Applications, ICCSA 2023

作者： Pham-Quoc, Cuong 268 Ly Thuong Kiet street District 10 Ho Chi Minh City Viet Nam Thu Duc Ho Chi Minh City Viet Nam

ISBN: (纸本)9783031371165

Recently, image/video-based applications have been widely used for many domains, such as traffic, medical, or robotics. In this context, IoT-based systems with video processing implemented on edge devices have been applied extensively, for example, surveillance, object detection and monitoring, or intelligent home/building systems. Although algorithms for images/videos encoder with various standards produce good results, they usually require high computing power that is limited with edge platforms. Therefore, we propose an efficient hardware/software codesign approach to accelerate the video encoder process with FPGA-based IoT edge computing platforms in this work. The design flow exploits the effectiveness of the high-level synthesis process to quickly and efficiently generate FPGA-based hardware accelerator cores to improve system performance. We use the H.264 encoder as our case study to verify the proposed design flow and evaluate the accelerator ability compared to general-purpose processors. An FPGA Ultra96-v2 edge computing board is used for conducting experiments with a certified dataset. Experimental results show that we obtain speed-ups by up to 14.9 × compared to a 4-core ARM processor. Our experimental system also saves up to 6.24 × energy consumption compared to the ARM processor. © 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Field programmable gate arrays (FPGA)

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Special Session: Estimation and Optimization of DNNs for Embedded Platforms

Special Session: Estimation and Optimization of DNNs for Emb...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Axel Jantsch Song Han Lin Meng Oliver Bringmann Haotian Tang Shang Yang Hengyi Li Matthias Wess Martin Lechner Christian Doppler Laboratory for Embedded Machine Learning TU Wien Vienna Austria Department of EECS Massachusetts Institute of Technology Cambridge MA USA Department of ECE Ritsumeikan University Kusatsu Shiga Japan Department of Computer Science University of Tübingen Tübingen Germany

ISBN: (数字)9798350356397

ISBN: (纸本)9798350356403

Several state of the art estimation and optimization techniques for CNNs and LLMs on embedded devices are summarized. For LLMs an Activation-aware Weight Quantization and on-the-fly dequantization techniques is presented. For CNNs various pruning algorithms and an integrated optimization and implementation flow is discussed. To estimate inference latency of CNNs on specific hardware platforms, three different techniques are reviewed: A mixed analytic-stochastic model, an analytic model based on step-wise linear functions, and a method that uses a detailed architecture description of the hardware.

关键词： Analytical models Quantization (signal) Estimation hardware Inference algorithms Optimization

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Extracting hardware Reconfiguration Models based on Knowledge synthesis from STEP Files

Extracting Hardware Reconfiguration Models based on Knowledg...

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acm/IEEE international conference on Model Driven Engineering Languages and systems (MODELS)

作者： Caesar, Birte Jansen, Nico Weigand, Maximilian Fay, Alexander Rumpe, Bernhard Helmut Schmidt Univ Inst Automat Technol Hamburg Germany Rhein Westfal TH Aachen Software Engn Aachen Germany

ISBN: (纸本)9798350324983

Today's industrial manufacturing challenges force manufacturers to optimize and increase the flexibility of their facilities. In practice, this requires analyzing, preparing for adaptation, and adapting brownfield manufacturing systems. The digital twin, a digital representation of a manufacturing system, is a key enabler for efficiency, flexibility, and sustainability. Unfortunately, the analysis and preparation of brownfield systems for adaptation, as well as the creation of digital twins, are challenging and time-consuming tasks. This paper presents an approach to automatically create digital models of systems based on 3D CAD models. To this end, the CAD data, stored as a STEP file, is analyzed to extract relevant information for a subsequent graph analysis, which is used to identify components, their dependencies, and the resulting functional modules. Finally, the gained knowledge is transformed into feature models that can be used as a digital model for configuration selection to support automatic reconfiguration planning of brownfield manufacturing systems. The developed approach is evaluated based on an industrial use case of a soft gripper system.

关键词： CAD data Reconfiguration Graph Analysis Adaptation Reengineering Digital Twin Digital Model

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Special Session: Emerging Architecture Design, Control, and Security Challenges in software Defined Vehicles

Special Session: Emerging Architecture Design, Control, and ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Aya El-Fatyany Xiaohang Wang Parasara Sridhar Duggirala Samarjit Chakraborty Sudeep Pasricha Amit Kumar Singh Zhejiang University Menoufia University UNC Chapel Hill Colorado State University University of Essex

ISBN: (数字)9798350356397

ISBN: (纸本)9798350356403

software Defined Vehicles (SDVs) represent a paradigm shift in the automotive industry, where vehicles are increasingly controlled and managed through software, while relying less on mechanical and hardware components. While this allows considerable flexibility in the introduction of new “smart” features and fast tracks innovations in multiple domains, it also creates new challenges and opportunities in architecture design, control, and security. By adopting modular architectures, adaptive control strategies, and robust security measures, SDVs can pave the way for a safer and more efficient future of transportation. In this paper, we cover perspectives from both, industry and academia, in this area. They provide embedded systems researchers an overview of recent developments and emerging challenges in SDV from the perspective of architecture design, control, and security. The emerging challenges also set the foundations for future research in this domain.

关键词： Industries Technological innovation Embedded systems Transportation Computer architecture software hardware Security Adaptive control Automotive engineering

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The RISC-V instruction set architecture optimization and fixed-point math library co-design: Work-in-progress 21

The RISC-V instruction set architecture optimization and fix...

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2021 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2021

作者： Liu, Meng Faculty of Information Technology School of Microelectronics Beijing University of Technology Beijing100124 China

ISBN: (纸本)9781450390767

In the field of IoT, RISC-V as an open-source instruction set shows great application potential. On the one hand, this is due to the low cost brought by the hardware open source trend. On the other hand, the modular instruction set architecture (ISA) design brings agile design ideas, and designers can pay more attention to the collaborative design of key ISA and software libraries. However, by analyzing the underlying mathematical assembly library, we found that the current RISC-V standard instruction set still has room for performance improvement for lightweight control mathematical operations. In this paper, we introduce a set of custom RISC-V ISA designs for fixed-point math libraries and perform performance evaluations to demonstrate the optimization results. © 2021 acm.

关键词： Open source software

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2017 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2017

2017 International Conference on Hardware/Software Codesign ...

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2017 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2017

ISBN: (纸本)9781450351850

The proceedings contain 24 papers. The topics discussed include: towards the application of flask security architecture to SoC design;a power-efficient and high performance FPGA accelerator for convolutional neural networks;a unified framework for throughput analysis of synchronous data flow graphs under memory constraints;data analytics enables energy-efficiency and robustness: from mobile to manycores, datacenters, and networks;a fast online sequential learning accelerator for IoT network intrusion detection;small neural nets are beautiful: enabling embedded systems with small deep-neural-network architectures;driving behavior modeling and estimation for battery optimization in electric vehicles;heterogeneous redundancy to address performance and cost in multi-core SIMT;a machine learning-based approach for power and thermal management of next-generation video coding on MPSoCs;IR-level annotation strategy dealing with aggressive loop optimizations for performance estimation in native simulation;retention state-aware energy management for efficient nonvolatile processors;communication optimization for thermal reliable many-core systems;significance-driven adaptive approximate computing for energy-efficient image processing application;and 3D nanosystems enable embedded abundant-data computing.

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Special Session: Neuro-Symbolic Architecture Meets Large Language Models: A Memory-Centric Perspective

Special Session: Neuro-Symbolic Architecture Meets Large Lan...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Mohamed Ibrahim Zishen Wan Haitong Li Priyadarshini Panda Tushar Krishna Pentti Kanerva Yiran Chen Arijit Raychowdhury Georgia Institute of Technology Purdue University Yale University University of California Berkeley Duke University

ISBN: (数字)9798350356397

ISBN: (纸本)9798350356403

Large language models (LLMs) have significantly transformed the landscape of artificial intelligence, demonstrating exceptional capabilities in natural language understanding and generation. Recently, the integration of LLMs with neurosymbolic architectures has gained traction to enhance contextual awareness and planning capabilities. However, this integration faces computational challenges that hinder scalability and efficiency, especially in edge computing environments. This paper provides an in-depth analysis of these challenges and explores state-of-the-art solutions, focusing on memory-centric computing principles at both algorithmic and hardware levels. Our exploration is centered around the key computational elements of the Transformer, the foundation of all LLMs, and vector-symbolic architecture, the leading neuro-symbolic model for edge applications. Additionally, we propose potential research directions for further investigation. By examining these aspects, this paper aims to bridge critical gaps in the path toward effective artificial general intelligence at the edge.

关键词： Computational modeling Scalability Large language models Focusing Computer architecture Transformers hardware Natural language processing Planning Optimization

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CODES+ISSS'12 - Proceedings of the 10th acm international conference on hardware/software-codesign and system synthesis, Co-located with ESWEEK

CODES+ISSS'12 - Proceedings of the 10th ACM International Co...

引用

10th acm international conference on hardware/software-codesign and system synthesis, CODES+ISSS 2012, Co-located with 8th Embedded systems Week, ESWEEK 2012

ISBN: (纸本)9781450314268

The proceedings contain 59 papers. The topics discussed include: a standards-based, fully-open software platform for smart embedded systems;research issues in smart phones, notepads and related services;ViPZonE: OS-level memory variability-driven physical address zoning for energy savings;dynamic transient fault detection and recovery for embedded processor datapaths;SPI-SNOOPER: a hardware-software approach for transparent network monitoring in wireless sensor networks;automatic extraction of multi-objective aware pipeline parallelism using genetic algorithms;managing latency in embedded streaming applications under hard-real-time scheduling;dynamic scheduling of stream programs on embedded multi-core processors;a distributed interleaving scheme for efficient access to wide IO DRAM Memory;DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs;and a traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture.

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LION Real-Time I/O Transfer Control for Massively Parallel Processor Arrays 21

LION Real-Time I/O Transfer Control for Massively Parallel P...

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19th acm-IEEE international conference on Formal Methods and Models for system Design (MEMOCODE)

作者： Walter, Dominik Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg Hardware Software Codesign Erlangen Germany

ISBN: (纸本)9781450391276

The performance of many accelerator architectures depends on the communication with external memory. During execution, new I/O data is continuously fetched forth and back to memory. This data exchange is very often performance-critical and a careful orchestration thus vital. To satisfy the I/O demand for accelerators of loop nests, it was shown that the individual reads and writes can be merged into larger blocks, which are subsequently transferred by a single DMA transfer. Furthermore, the order in which such DMA transfers must be issued, was shown to be reducible to a real-time task scheduling problem to be solved at run time. Rather than just concepts, we investigate in this paper efficient algorithms, data structures and their implementation in hardware of such a programmable Loop I/O Controller architecture called LION that only needs to be synthesized once for each processor array size and I/O buffer configuration, thus supporting a large class of processor arrays. Based on a proposed heap-based priority queue, LION is able to issue every 6 cycles a new DMA request to a memory bus. Even on a simple FPGA prototype running at just 200 MHz, this allows for more than 33 million DMA requests to be issued per second. Since the execution time of a typical DMA request is in general at least one order of magnitude longer, we can conclude that this rate is sufficient to fully utilize a given memory interface. Finally, we present implementations on FPGA and also 22nm FDX ASIC showing that the overall overhead of a LION typically amounts to less than 5% of an overall processor array design.

关键词： Massively Parallel Processor Arrays TCPA I/O Scheduling Data Transfers Priority QueueZ

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