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Slack analysis in the system design loop 08

Slack analysis in the system design loop

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Embedded systems Week 2008 - 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Venkataramani, Girish Goldstein, Seth C. ECE Department Carnegie Mellon University Pittsburgh PA United States School of Computer Science Carnegie Mellon University Pittsburgh PA United States

ISBN: (纸本)9781605584706

We present a system-level technique to analyze the impact of design optimizations on system-level timing dependencies. This technique enables us to speed up the design cycle by substituting, in the design the loop, the time-consuming simulation step with a fast timing update routine. As a result, we can significantly reduce the design time from on the order of hours/days to the order of seconds/minutes. The update algorithm is defined on the Transaction Level Model (TLM) and can be used by any design flow that invokes TLM-based optimizations. This algorithm has linear-time complexity in the program size and experimental results indicate that any loss of accuracy due to this technique is negligible (

关键词： systems analysis

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A time-predictable system initialization design for huge-capacity flash-memory storage systems 08

A time-predictable system initialization design for huge-cap...

引用

Embedded systems Week 2008 - 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Wu, Chin-Hsien Department of Electronic Engineering National Taiwan University of Science and Technology Taipei Taiwan

ISBN: (纸本)9781605584706

The capacity of flash-memory storage systems grows at a speed similar to many other storage systems. In order to properly manage the product cost, vendors face serious challenges in system designs. How to provide an expected system initialization time for huge-capacity flash-memory storage systems has become an important research topic. In this paper, a time-predictable system initialization design is proposed for huge-capacity flash-memory storage systems. The objective of the design is to provide an expected system initialization time based on a coarse-grained flash translation layer. The time-predictable analysis of the design is provided to discuss the relation between the size of main memory and the system initialization time. The system initialization time can be also estimated and predicted by the time-predictable analysis. Copyright 2008 acm.

关键词： Flash memory

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Model checking systemC designs using timed automata 08

Model checking SystemC designs using timed automata

引用

Embedded systems Week 2008 - 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Herber, Paula Fellmuth, Joachim Glesner, Sabine Software Engineering for Embedded Systems Group Technical University of Berlin Germany

ISBN: (纸本)9781605584706

systemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify systemC designs. In this paper, we present an approach to overcome this problem by defining the semantics of systemC by a mapping from systemC designs into the well-defined semantics of UPPAAL timed automata. The informally defined behavior and the structure of systemC designs are completely preserved in the generated UPPAAL models. The resulting UPPAAL models allow us to use the UPPAAL model checker and the UPPAAL tool suite, including simulation and visualization tools. The model checker can be used to verify important properties such as liveness, deadlock freedom or compliance with timing constraints. We have implemented the presented transformation, applied it to two examples and verified liveness, safety and timing properties by model checking, thus showing the applicability of our approach in practice. Copyright 2008 acm.

关键词： Semantics

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Concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design 08

Concurrency emulation and analysis of parallel applications ...

引用

Embedded systems Week 2008 - 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Beltrame, Giovanni Fossati, Luca Sciuto, Donatella European Space Agency Keplerlaan 1 Noordwijk Netherlands Politecnico di Milano Piazza Leonardo da Vinci Milano Italy

ISBN: (纸本)9781605584706

This paper presents a novel technique for the modeling and the simulation of parallel applications for Multi-Processor systems-on-Chip (MPSoCs). This technique consists of an application-transparent emulation of OS primitives, includ-ing task creation, scheduling, synchronization etc.;this emu-lation guarantees compatibility with any program compiled against the standard POSIX library, independently of the target OS. This methodology can be used to perform initial HW/SW partitioning and concurrent engineering of a given application, as it allows any software routine to be trans-parently emulated with systemC modules. The proposed approach has been verified on a large set of multi-threaded benchmarks, with both POSIX Threads and OpenMP pro-gramming styles. Results show that our methodology en-ables (a) fast simulation of POSIX applications, (b) accurate analysis of multi-threaded applications, and (c) co-design and fast preliminary hardware-software partitioning. This work has been partially supported by the European HiPEAC network of excellence. Copyright 2008 acm.

关键词： system-on-chip

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Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation 08

Combination of instruction set simulation and abstract RTOS ...

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Embedded systems Week 2008 - 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Krause, Matthias Englert, Dominik Bringmann, Oliver Rosenstiel, Wolfgang FZI Forschungszentrum Informatik Haid-und-Neu-Str. 10-14 76131 Karlsruhe Germany Universität Tübingen Sand 13 72076 Tübingen Germany

ISBN: (纸本)9781605584706

Instruction set simulation and real time operating system modeling have become important issues for the design of distributed embedded systems. This paper presents a holistic approach to simulate a distributed, embedded system that includes target software, processing units, and abstract RTOS within a virtual prototype environment. The processing unit is modeled by an ISS, which is embedded in a systemC environment to allow the integration into a platform model. In comparison to existing approaches, the RTOS is not directly running on the ISS but outsourced and replaced by an RTOS model. This step strongly reduces simulation time since the execution on the ISS is much more time consuming in contrast to the execution on the host processor. The results show the theoretical and measured performance gain depending on the RTOS scheduler and task switching. Copyright 2008 acm.

关键词： Embedded systems

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software optimization for MPSoC: A MPEG-2 decoder case study 08

Software optimization for MPSoC: A MPEG-2 decoder case study

引用

Embedded systems Week 2008 - 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Cheung, Eric Hsieh, Harry Balarin, Felice Dept. of Computer Science and Engineering University of California Riverside Riverside CA 92521 United States Cadence Design Systems San Jose CA 95134 United States

ISBN: (纸本)9781605584706

Using traditional software profiling to optimize embedded software in an MPSoC design is not reliable. With multiple processors running concurrently and programs interacting, traditional profiling on individual processors cannot capture useful execution information to assist software optimization. A new method to model parallel executions of interacting programs is needed. In this paper, we consider the software optimization problem for throughput-constrained MPSoC designs. We define the "longest delay path" as a sequence of steps leading to a throughput constraint violation and propose an algorithm to build up the path dynamically during simulation. Using an industrial-strength MPEG-2 decoder design in our case study and custom instructions for software optimization, we show that we can optimize the software efficiently in MPSoC designs using frequently executed statement information from the longest delay path. Copyright 2008 acm.

关键词： Decoding

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Static analysis for Fast and accurate design space exploration of caches 08

Static analysis for Fast and accurate design space explorati...

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Embedded systems Week 2008 - 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Liang, Yun Mitra, Tulika Department of Computer Science National University of Singapore Singapore

ISBN: (纸本)9781605584706

Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in particular trace-driven simulation, is widely used to estimate cache hit rates. However, simulation is too slow to be deployed in the design space exploration, specially when it involves hundreds of design points and huge traces or long program execution. In this paper, we propose a novel static analysis technique for rapid and accurate design space exploration of instruction caches. Given the program control flow graph (CFG) annotated only with basic block and control flow edge execution counts, our analysis estimates the hit rates for multiple cache configurations in one pass. We achieve this by modeling the cache states at each node of the CFG in probabilistic manner and exploiting the structural similarities among related cache configurations. Experimental results indicate that our analysis is 24-3, 855 times faster compared to the fastest known cache simulator while maintaining high accuracy (0.7% average error), in predicting hit rates for popular embedded benchmarks. Copyright 2008 acm.

关键词： system-on-chip

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Extending Open Core Protocol to support system-level cache coherence 08

Extending Open Core Protocol to support system-level cache c...

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Embedded systems Week 2008 - 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Aisopos, Konstantinos Chou, Chien-Chun Peh, Li-Shiuan Dept. of Electrical Engineering Princeton University Princeton NJ 08544 United States Sonics Inc. Milpitas CA 95035 United States

ISBN: (纸本)9781605584706

Open Core Protocol (OCP) is a standard on-chip core interface specification. The current release is flexible and configurable to support the communication needs of a wide range of Intellectual Property cores, and is now in widespread use. However, it does not support system-level coherence. This paper summarizes an effort within the OCP-IP cache coherence working group on incorporating cache coherence extensions into OCP, which is expected to have strong impact on the MPSoC industry. In this paper, we propose a backward-compatible coherent Open Core Protocol interface and discuss the design challenges and implications introduced. This interface is flexible and can support a range of coherence protocols and schemes: we show how it can specify a snoopy bus-based scheme as well as a directory-based scheme. The correctness of the specification and models was verified using NuSMV, via exploring the entire state space for the two basic coherence schemes. Copyright 2008 acm.

关键词： Specifications

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Scratchpad allocation for concurrent embedded software 08

Scratchpad allocation for concurrent embedded software

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Embedded systems Week 2008 - 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Suhendra, Vivy Roychoudhury, Abhik Mitra, Tulika Department of Computer Science National University of Singapore Singapore

ISBN: (纸本)9781605584706

software-controlled scratchpad memory is increasingly employed in embedded systems as it offers better timing predictability compared to caches. Previous scratchpad allocation algorithms typically consider single process applications. But embedded applications are mostly multi-tasking with real-time constraints, where the scratchpad memory space has to be shared among interacting processes that may preempt each other. In this paper, we develop a novel dynamic scratchpad allocation technique that takes these process interferences into account to improve the performance and predictability of the memory system. We model the application as a Message Sequence Chart (MSC) to best capture the interprocess interactions. Our goal is to optimize the worst-case response time (WCRT) of the application through runtime reloading of the scratchpad memory content at appropriate execution points. We propose an iterative allocation algorithm that consists of two critical steps: (1) analyze the MSC along with the existing allocation to determine potential interference patterns, and (2) exploit this interference information to tune the scratchpad reloading points and content so as to best improve the WCRT. We evaluate our memory allocation scheme on a real-world embedded application controlling an Unmanned Aerial Vehicle (UAV). Copyright 2008 acm.

关键词： Embedded systems

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synthesis of heterogeneous pipelined multiprocessor systems using ILP: JPEG case study 08

Synthesis of heterogeneous pipelined multiprocessor systems ...

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Embedded systems Week 2008 - 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Javaid, Haris Parameswaran, Sri School of Computer Science and Engineering University of New South Wales Sydney Australia

ISBN: (纸本)9781605584706

Streaming applications can be implemented with a pipeline of processors. Each processor in the pipeline can be an Application Specific Instruction Set Processor (ASIP) with the result being a heterogeneous pipelined MPSoC system. Since ASIPs can be of differing configurations, finding the optimal set of configurations for a multiprocessor architecture is a difficult problem. In this paper, we obtain an optimal system design for a set of processors which execute a multimedia application. The variables in the system are the presence or absence of different additional instructions and differing cache configurations for each of the processors. The problem is formulated as a 0-1 Integer Linear Programming (ILP) problem. To reduce the complexity of the ILP formulation, inferior ASIP configurations are efficiently pruned so that the solution could be reached quickly. Given a system runtime constraint, the proposed methodology finds a design with minimal area. We integrated this design methodology into a commercial design flow, and performed a case study upon the JPEG encoding application. We obtained 15 optimal designs subject to 15 different runtime constraints, each in less than 100 seconds from more than 4.2 × 10 13 design points. Copyright 2008 acm.

关键词： Pipelines

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