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Methodology for multi-granularity embedded processor power model generation for an ESL design flow 08

Methodology for multi-granularity embedded processor power m...

引用

Embedded systems Week 2008 - 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Park, Young-Hwan Pasricha, Sudeep Kurdahi, Fadi J. Dutt, Nikil University of California Irvine CA United States Colorado State University Fort Collins CO United States

ISBN: (纸本)9781605584706

With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is critical for these processor power models to be useable across various modeling abstractions in an electronic system level (ESL) design flow, to guide early design decisions. In this paper, we propose a unified processor power modeling methodology for the creation of power models at multiple granularity levels that can be quickly mapped to an ESL design flow. Our experimental results based on applying the proposed methodology on an OpenRISC processor demonstrate the usefulness of having multiple power models. The generated models range from very high-level two-state and architectural/ISS models that can be used in transaction level models (TLM), to extremely detailed cycle-accurate models that enable early exploration of power optimization techniques. These models offer a designer tremendous flexibility to trade off estimation accuracy with estimation/simulation effort. Copyright 2008 acm.

关键词： system-on-chip

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system-level mitigation of WID leakage power variability using body-bias islands 08

System-level mitigation of WID leakage power variability usi...

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Embedded systems Week 2008 - 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Garg, Siddharth Marculescu, Diana Dept. of Electrical and Computer Engineering Carnegie Mellon University United States

ISBN: (纸本)9781605584706

Adaptive Body Biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ABB technique can be improved by partitioning a design into a number of "body-bias islands," each with its individual body-bias voltage. In this paper, we propose a system-level leakage variability mitigation framework to partition a multiprocessor system into body-bias islands at the processing element (PE) granularity at design time, and to optimally assign body-bias voltages to each island post-fabrication. As opposed to prior gate- and circuit-level partitioning techniques that constrain the global clock frequency of the system, we allow each island to run at a different speed and constrain only the relevant system performance metrics - in our case the execution deadlines. Experimental results show the efficacy of the proposed framework in reducing the mean and standard deviation of leakage power dissipation compared to a baseline system without ABB. At the same time, the proposed techniques provide significant runtime improvements over a previously proposed Monte-Carlo based technique while providing similar reductions in leakage power dissipation. Copyright 2008 acm.

关键词： Bias voltage

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Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors

Yield maximization for system-level task assignment and conf...

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Embedded systems Week 2008 - 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Singhal, Love Oh, Sejong Bozorgzadeh, Eli Center for Embeddded Computer Systems University of California Irvine United States Korea Advanced Institute of Science and Technology Daejeon Korea Republic of

ISBN: (纸本)9781605584706

Configurable multiprocessor system is a promising design alternative because of its high degree of flexibility, short development time, and potentially high performance under constraints and challenges driven by applications. An important design challenge at 45nm for multi-core system is manufacturing process variation. Due to increasing concern of WID variation, designers will have to choose configurations of processing cores that maximize yield of the system while not affecting performance and throughput constraints. Due to interdependency between processor configuration selection and task allocation and its impact on yield and latency constraints, we tackle both problems simultaneously. In this paper, we propose the problem of task allocation and configuration selection for yield optimization. We prove the problem is NP-hard and propose an optimal pseudo-polynomial on Serial-Parallel graphs. We target streaming applications in pipelined reconfigurable multiprocessor systems. We provide a case study of configurable Leon processors as the cores implemented on FPGA. Results show that proposed problem could result in significant improvement of the timing yield of the system by exploiting extra slack on tasks. Copyright 2008 acm.

关键词： Optimization

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Reliable performance analysis of a multicore multithreaded system-on-chip 08

Reliable performance analysis of a multicore multithreaded s...

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Embedded systems Week 2008 - 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Schliecker, Simon Negrean, Mircea Nicolescu, Gabriela Paulin, Pierre Ernst, Rolf Technische Universität Braunschweig Germany Ecole Polytechnique de Montreal Canada ST Microelectronics Ottawa Canada

ISBN: (纸本)9781605584706

Formal performance analysis is now regularly applied in the design of distributed embedded systems such as automotive electronics, where it greatly contributes to an improved predictability and platform robustness of complex networked systems. Even though it might be highly beneficial also in MpSoC design, formal performance analysis could not easily be applied so far, because the classical task communication model does not cover processor-memory traffic, which is an integral part of MpSoC timing. Introducing memory accesses as individual transactions under the classical model has shown to be inefficient, and previous approaches work well only under strict orthogonalization of different traffic streams. Recent research has presented extensions of the classical task model and a corresponding analysis that covers performance implications of shared memory traffic. In this paper we present a multithreaded multiprocessors platform and multimedia application. We conduct performance analysis using the new analysis options and specifically benchmark the quality of the available approach. Our experiments show that corner case coverage can now be supplied with a very high accuracy, allowing to quickly investigate architectural alternatives. Copyright 2008 acm.

关键词： system-on-chip

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Intra- and inter-processor hybrid performance modeling for MPSoC architectures 08

Intra- and inter-processor hybrid performance modeling for M...

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Embedded systems Week 2008 - 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2008

作者： Ophelders, Frank E.B. Chakraborty, Samarjit Corporaal, Henk Department of Electrical Engineering Technische Universiteit Eindhoven Netherlands Department of Computer Science National University of Singapore Singapore

ISBN: (纸本)9781605584706

The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid performance model-ing techniques. Here, the idea is to apply different modeling and analysis techniques to different subsystems/components of an ar-chitecture/application. Such hybrid techniques often turn out to be more efficient and accurate compared to relying on a single analy-sis technique for the entire system. However, the challenge asso-ciated with this approach is to combine the different analysis re-sults effectively to obtain conservative performance estimates for the entire system. In this paper we study a hybrid scheme where certain system components are simulated (e.g. using instruction set simulators), whereas others are analyzed using a formal tech-nique called Real-Time Calculus (RTC). The main novelty of our approach stems from our use of this hybrid technique even for mul-tiple tasks mapped onto a single processing element. In contrast to this, previous approaches relied on either full simulation or RTC-based analysis for an entire architectural component (e.g. a proces-sor or a bus). The techniques we develop in this paper therefore al-low for both intra- and inter-processor hybrid performance model-ing and show how the different analysis results can be combined to efficiently obtain tight performance estimates for complex MPSoC architectures. We demonstrate the usefulness of this approach us-ing an MPEG-2 decoder application that is partitioned and mapped onto two processing elements connected by FIFO buffers. Copyright 2008 acm.

关键词： system-on-chip

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HW/SW auto-coupling for fast IP integration in SoC designs

HW/SW auto-coupling for fast IP integration in SoC designs

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5th international conference on Embedded software and systems

作者： Hwang, Yin-Tsung Chen, Jun-Yen Chiu, Jun-Jieh Natl Chung Hsing Univ Dept Elect Engn Taichung 40201 Taiwan

ISBN: (纸本)9780769532875

IP intergration in SoC nowadays contains two design aspects, i.e. hardware interface and software driver. The hardware interface supports necessary signal mapping, protocol translation and data buffering so that an IP can adapt to various system architectures. The software driver provides IP access controls from the software domain in the presence of operating system. The automation of both design processes in a coupling manner is addressed in this paper. We first outline the methodology of automatic interface synthesis and elaborate on the topics of signal mapping, protocol conversion and interface template architecture. We next present the framework of a baseline driver generator and detail the generation schemes of basic file operations and other functions and driver settings. Both tools are linked to form a HW/SW auto-coupling design suite, which features minimum user knowledge toward the hardware and OS details in usage. Some design examples on the interface synthesis tool and an JPEG codec HW/SW codesign example on the integrated design suite are provided to prove the effectiveness of the proposed system.

关键词： system-on-chip

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Latency-insensitive hardware/software interfaces 08

Latency-insensitive Hardware/Software interfaces

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6th acm/IEEE international conference on Formal Methods and Models for Co-Design

作者： Hoover, Greg Brewer, Forrest Gill, Chris Univ Calif Santa Barbara Santa Barbara CA 93106 USA Washington Univ Washington DC 63130 USA

ISBN: (纸本)9781424424177

Modern embedded system designers face challenges of unprecedented scales, creating systems that integrate functionality spanning disparate scientific domains, with increasing computation demands and ever-stricter power requirements. Meeting the constraints of these systems requires practical design flows that reduce development time without sacrificing design efficiency. Novel design description methodologies coupled with automated and semi-automated synthesis paths greatly accelerate the design of modern hardware systems. In the software space, however, synthesis methods are far from producing co-designs with the necessary efficiency. This is particularly evident at the hardware/software boundary, where the tight coupling of low-level firmware routines and hardware protocols require designers to have deep design knowledge in both domains. To address this issue, we propose a latency-insensitive software execution model that allows direct connection to elastic hardware control topologies.

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Vision: Testing of mechatronics software using agile simulation

Vision: Testing of mechatronics software using agile simulat...

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3rd international Workshop on Automation of software Test, AST 2008, held in Conjunction with the 30th international conference on software Engineering, ICSE 2008

作者： Masticola, Stephen P. Gall, Michael Siemens Corporate Research 755 College Road East Princeton NJ 08540 United States

ISBN: (纸本)9781605580302

Mechatronics is the practice of creating systems that synergize electrical, mechanical, and software technology. With few exceptions, testing software that is embedded in mechatronics systems has historically been done only with the hardware in the loop (HIL). There are many disadvantages to HIL testing, including cost, schedule delays, and resource bottlenecks. Ironically, cost and schedule delays are also often seen by technical managers as impediments to simulating the mechatronics hardware. We present a vision for agile simulation, with the intent to lower the cost and time barriers of simulating mechatronics hardware to test software. Some key ideas include: focus on validating the software alone, rather than the entire system;doing the minimum amount of dynamic modeling needed to test the software;work even with legacy systems that might not have been designed with testability in mind;leverage existing tools wherever possible;support stubbing out the hardware using agile techniques such as refactoring and test-driven development. Copyright 2008 acm.

关键词： hardware-software codesign

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SoC-C: Efficient programming abstractions for heterogeneous multicore systems on chip

SoC-C: Efficient programming abstractions for heterogeneous ...

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Embedded systems Week 2008 - 2008 international conference on Compilers, Architecture and synthesis for Embedded systems, CASES'08

作者： Reid, Alastair D. Flautner, Krisztian Grimley-Evans, Edmund Lin, Yuan ARM Ltd. United Kingdom University of Michigan United States

ISBN: (纸本)9781605584690

The architectures of system-on-chip (SoC) platforms found in high-end consumer devices are getting more and more complex as designers strive to deliver increasingly compute-intensive applications on near-constant energy budgets. Workloads running on these platforms require the exploitation of heterogeneous parallelism and increasingly irregular memory hierarchies. The conventional approach to programming such hardware is very low-level but this yields software which is intimately and inseparably tied to the details of the platform it was originally designed for, limiting the software's portability, and, ultimately, the architectural choices available to designers of future platform generations. The key insight of this paper is that many of the problems experienced in mapping applications onto SoC platforms come not from deciding how to map a program onto the hardware but from the need to restructure the program and the number of interdependencies introduced in the process of implementing those decisions. We tackle this complexity with a set of language extensions which allows the programmer to introduce pipeline parallelism into sequential programs, manage distributed memories, and express the desired mapping of tasks to resources. The compiler takes care of the complex, error-prone details required to implement that mapping. We demonstrate the effectiveness of SoC-C and its compiler with a "software defined radio" example (the PHY layer of a Digital Video Broadcast receiver) achieving a 3.4x speedup on 4 cores. Copyright 2008 acm.

关键词： system-on-chip

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Session details: Analysis of parallel application and architecture synthesis 08

Session details: Analysis of parallel application and archit...

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Proceedings of the 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Sungjoo Yoo Grant Martin POSTECH South Korea Tensilica

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ISBN: (纸本)9781605584706

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