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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

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Session details: system level power modeling and optimization 08

Session details: System level power modeling and optimizatio...

引用

Proceedings of the 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Ann Gordon-Ross Roman Lysecky University of Florida USA University of Arizona

No abstract available.

ISBN: (纸本)9781605584706

No abstract available.

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Session details: system level design: throughput, dependability, coherence, and yield 08

Session details: System level design: throughput, dependabil...

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Proceedings of the 6th IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Prabhat Mishra Frank Vahid University of Florida USA University of California at Riverside

No abstract available.

ISBN: (纸本)9781605584706

No abstract available.

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Proceedings - 6th acm and IEEE international conference on Formal Methods and Models for Co-Design, MEMOCODE'08

Proceedings - 6th ACM and IEEE International Conference on F...

引用

6th acm and IEEE international conference on Formal Methods and Models for Co-Design, MEMOCODE'08

ISBN: (纸本)9781424424177

The proceedings contain 19 papers. The topics discussed include: programming multicores with Kahn process networks;a choice;arithmetic circuits verification without looking for internal equivalences;from data to events: checking properties on the control of a system;vacuity analysis by fault simulation;rule-based approaches for equivalence checking of specC programs;static deadlock detection for the SHIM concurrent language;a comparison of two systemC/TLM semantic for formal verification;latency-insensitive hardware/software interfaces;directed-logical testing for functional verification of microprocessors;estimating the performance of cache replacement policies;and on the deterministic multi-threaded software synthesis for polychronous specifications.

关键词： Concurrency control

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Architecture of Computing systems - ARCS 2008: 21st international conference: Proceedings

引用

21st international conference on Architecture of Computing systems, ARCS 2008

ISBN: (纸本)3540781528

The proceedings contain 19 papers. The topics discussed include: system level simulation of autonomic SoCs with TAPES;topology-aware replica placement in fault-tolerant embedded networks;design of gate array circuits using evolutionary algorithms;a hardware packet re-sequencer unit for network processors;dynamic reconfiguration of FlexRay schedules for response time reduction in asynchronous fault-tolerant networks;synthesis of multi-dimensional high-speed FIFOs for out-of-order communication;a novel routing architecture for field-programmable gate-arrays;a predictable simultaneous multithreading scheme for hard real-time;soft real-time scheduling on SMT processors with explicit resource allocation;and a hardware/software codesign of a co-processor for real-time hyperelliptic curve cryptography on a Spartan3 FPGA.

关键词： Field programmable gate arrays (FPGA)

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Formal Methods for the Analysis and synthesis of Nanometer-Scale Cellular Arrays

Formal Methods for the Analysis and Synthesis of Nanometer-S...

引用

international conference on Computer Aided Design (ICCAD 06)

作者： Carmona, Josep Cortadella, Jordi Takada, Yousuke Peper, Ferdinand Univ Politecn Cataluna Software Dept ES-08034 Barcelona Spain Canopus Co Ltd Nishi Ku Kobe Hyogo 6512241 Japan Natl Inst Informat & Commun Technol Nano ICT Grp Nishi Ku Kobe Hyogo 6512492 Japan

Nanometer-scale structures suitable for computing have been investigated by several research groups in recent years. A common feature of these structures is their dynamic evolution through cascaded local interactions embedded on a discrete grid. Finding configurations capable of conducting computations is a task that often requires tedious experiments in laboratories. Formal methods-though used extensively for the specification and verification of software and hardware computing systems-are virtually unexplored with respect to computational structures at atomic scales. This paper presents a systematic approach toward the application of formal methods in this context, using techniques like abstraction, model-checking, and symbolic representations of states to explore and discover computational structures. The proposed techniques are applied to a system of CO molecules on a grid of Copper atoms, resulting in the design of a complete library of combinational logic gates based on this molecular system. The techniques are also applied on (more general) systems of cellular automata that employ an asynchronous mode of timing. The use of formal methods may narrow the gap between Physical Chemistry and Computer Science, allowing the description of interactions of nanometer scale systems on a level of abstraction suitable to devise computing devices.

关键词： Nanocomputing cellular array model checking symbolic techniques

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Latency-Insensitive hardware/software Interfaces

Latency-Insensitive Hardware/Software Interfaces

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Greg Hoover Forrest Brewer Chris Gill University of California USA Santa Barbara and Washington University

Modern embedded system designers face challenges of unprecedented scales, creating systems that integrate functionality spanning disparate scientific domains, with increasing computation demands and ever-stricter power requirements. Meeting the constraints of these systems requires practical design flows that reduce development time without sacrificing design efficiency. Novel design description methodologies coupled with automated and semi-automated synthesis paths greatly accelerate the design of modern hardware systems. In the software space, however, synthesis methods are far from producing co-designs with the necessary efficiency. This is particularly evident at the hardware/software boundary, where the tight coupling of low-level firmware routines and hardware protocols require designers to have deep design knowledge in both domains. To address this issue, we propose a latency-insensitive software execution model that allows direct connection to elastic hardware control topologies.

关键词： hardware Embedded software Timing Embedded system Embedded computing software systems Communication system control Computer interfaces Design methodology Acceleration

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HW/SW Auto-Coupling for Fast IP Integration in SoC Designs

HW/SW Auto-Coupling for Fast IP Integration in SoC Designs

引用

international conference on Embedded software and systems

作者： Yin-Tsung Hwang Jun-Yen Chen Jun-Jieh Chiu Department of Electrical Engineering National Chung Hsing University Taichung Taiwan

ISBN: (纸本)9780769532875

IP intergration in SoC nowadays contains two design aspects, i.e. hardware interface and software driver. The hardware interface supports necessary signal mapping, protocol translation and data buffering so that an IP can adapt to various system architectures. The software driver provides IP access controls from the software domain in the presence of operating system. The automation of both design processes in a coupling manner is addressed in this paper. We first outline the methodology of automatic interface synthesis and elaborate on the topics of signal mapping, protocol conversion and interface template architecture. We next present the framework of a baseline driver generator and detail the generation schemes of basic file operations and other functions and driver settings. Both tools are linked to form a HW/SW auto-coupling design suite, which features minimum user knowledge toward the hardware and OS details in usage. Some design examples on the interface synthesis tool and an JPEG codec HW/SW codesign example on the integrated design suite are provided to prove the effectiveness of the proposed system.

关键词： Driver circuits Protocols hardware IP networks Converters Generators Signal mapping

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Virtual prototyping AADL architectures in a polychronous model of computation

Virtual prototyping AADL architectures in a polychronous mod...

引用

6th IEEE/acm international conference on Formal Methods and Models for codesign (MEMOCODE'08)

作者： Yue Ma Jean-Pierre Talpin Thierry Gautier INRIA Unitede Recherche Rennes-Bretagne-Atlantique Campus de Beaulieu Rennes France

While synchrony and asynchrony are two distinct concepts of concurrency theory, effective and formally defined embedded system design methodologies usually mix the best from both synchronous and asynchronous worlds by considering locally synchronous processes composed in a globally asynchronous way to form so called GALS architectures. In the avionics domain, for instance, the Architecture Analysis and Design Language (AADL) may be used to describe both the hardware and software architecture of an application at system-level. Yet, a synchronous design formalism might be preferred to model and validate each of the critical components of the architecture in isolation. In this paper, we illustrate the use of the polychronous (multi-clocked synchronous) paradigm to model partially asynchronous applications. The specification formalism SIGNAL is used to describe real-world avionic applications using concepts of Integrated Modular Avionics (IMA). We show how an AADL architecture can be automatically translated into a synchronous model in SIGNAL using these modeling concepts. We present a case study on the design of generic system architecture. The approach is being implemented in the framework of the ANR project TopCased.

关键词： Virtual prototyping Computer architecture Computational modeling Aerospace electronics Application software Concurrent computing Embedded system Design methodology hardware software architecture

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[Title page - 2008 6th acm/IEEE international conference on Formal Methods and Models for Co-Design]

[Title page - 2008 6th ACM/IEEE International Conference on ...

引用

acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

The following topics are dealt with: arithmetic circuits verification; semantics of system description languages; latency-insensitive hardware-software interfaces; on-the-fly equivalence checker based on Boolean equation systems; directed-logical testing for functional verification of microprocessors; deterministic multithreaded software synthesis from polychronous specifications; fault-tolerant real-time scheduler; LambdaRAM verification; wide-area distributed cache for high performance computing; on-chip communication design; and Bluespec systemVerilog.

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Classification of General Data Flow Actors into Known Models of Computation

Classification of General Data Flow Actors into Known Models...

引用

acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Christian Zebelein Joachim Falk Christian Haubelt Jurgen Teich Hardware Software CoDesign University of Erlangen Nuremberg Erlangen Germany

Applications in the signal processing domain are often modeled by data flow graphs which contain both dynamic and static data flow actors due to heterogeneous complexity requirements. Thus, the adopted notation to model the actors must be expressive enough to accommodate dynamic data flow actors. On the other hand, treating static data flow actors like dynamic ones hinders design tools in applying domain-specific optimization methods to static parts of the model, e.g., static scheduling. In this paper, we present a general notation and a methodology to classify an actor expressed by means of this notation into the synchronous and cyclo-static dataflow models of computation. This enables the use of a unified descriptive language to express the behavior of actors while still retaining the advantage to apply domain-specific optimization methods to parts of the system. In experiments we could improve both latency and throughput of a general data flow graph application using our proposed automatic classification in combination with a static single-processor scheduling approach by 57%.

关键词： Computational modeling Data flow computing Flow graphs Decoding Automata Signal processing algorithms Production Optimization methods Algorithm design and analysis Processor scheduling

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