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3rd international conference on Mobile Multimedia Communications, MobiMedia 2007

作者： Voros, Nikolaos S. Masselos, Konstantinos Dept. of Communication Systems and Networks TEl of Mesolonghi Ethniki Odos Antiriou Nafpaktou Varia Nafpaktos30300 Greece Dept. of Computer Science and Technology University of Peloponnese Terma Karaiskaki Tripolis22100 Greece

ISBN: (纸本)9789630626705

Wireless Local Area Networks (WLANs) are currently considered as one of the most popular application domains. In this paper the protyping of a WLAN system on a platform including microprocessors and FPGAs is described. The prototyping started from architecture exploration using a C++ library for hardware/software codesign. The developed prototype allowed evaluation of the system performance and the architecture decisions. The use of the systematic architecture exploration allowed making correct decisions early in the design cycle thus avoiding time consuming iterations from lower design stages (necessary when constraints are not met by the final implementation). Copyright 2007 ICST.

关键词： hardware-software codesign

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First IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2000

First IEEE/ACM/IFIP International Conference on Hardware/Sof...

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First IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2003

The proceedings contains 38 papers from the First IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2003. The topics discussed include: RTOS scheduling in transaction level models;hardware support for real-time operating systems;a fast parallel Reed-Solomon decoder on a reconfigurable architecture;a low power scheduler using game theory;programmers' views of SoCs;and verification of design decisions in ForSyDe.

关键词： Computer operating systems

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Predictable real-time software synthesis

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REAL-TIME systemS 2007年第3期36卷 159-198页

作者： Huang, Jinfeng Voeten, Jeroen Corporaal, Henk Eindhoven Univ Technol NL-5600 MB Eindhoven Netherlands Embedded Syst Inst Eindhoven Netherlands

Formal theories for real-time systems (such as timed process algebra, timed automata and timed petri nets) have gained great success in the modeling of concurrent timing behavior and in the analysis of real-time properties. However, due to the ineliminable timing differences between a model and its realization, synthesizing a software realization from a model in a predictable way is still a challenging research topic. In this article, we tackle this problem by solving a set of sub-problems. The solution is based on the theoretical results for property prediction proposed in Huang et al. (2003, Real-time property preservation in approximations of timed systems. In: Proceedings of 1st acm and IEEE international conference on formal methods and models for codesign. IEEE Computer Society, Los Alamitos, pp 163-171) and Huang (2005, Predictability in real-time system design. PhD thesis, Eindhoven University of Technology, The Netherlands), where quantitative property relations are established between two absolute/relative "close" real-time systems. This theory basically implies that if two systems are "close", they enjoy "similar" properties. These results cannot be directly applied in practice though, because a model and its realization typically have infinitely large absolute and relative timing differences. We show that this infinite time gap can be bridged through a sequence of carefully constructed intermediate time domains. Then the property-prediction results can be applied to any pair of adjacent time domains in the sequence. Consequently, real-time properties of the implementation can be predicted from the model. We propose two parameterized hypotheses to characterize the timing differences in the sequence and to guide a correctness-preserving design process. It is shown that these hypotheses can be incorporated in a concrete tool set. We demonstrate the feasibility of the predictable synthesis approach through the design of a railroad crossing system.

关键词： real-time systems formal methods program synthesis

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Improving the COWLS algorithm for hardware software co-synthesis of wireless client-server systems using preference vectors and peak power information 07

Improving the COWLS algorithm for hardware software co-synth...

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international conference on Computer systems and Technologies and Workshop for PhD Students in Computing, CompSysTech '07

作者： Hassani, Mohammad Mehdi Berangi, Reza Department of Computer Systems University of Islamic Azad Iran Department of Computer Systems Iran University of Science and Technologhy Iran

ISBN: (纸本)9789549641509

Embedded systems are used all over our society. Current estimates indicate that over 90 percent of worldwide computers are embedded systems [1]. As the complexity of system design increases, use of pre-designed components, provides an effective way to reduce the complexity of synthesized hardware. hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules in order to meet performance, power consumption and cost goals. While the design problem of systems that contain processors and ASIC chips is not new, computer aided synthesis of such heterogeneous or mixed systems poses challenging problems because of the differences in model and rate of computation by application-specific hardware and processor software. One of the areas that are investigated recently is the simultaneous co-synthesis of client and server processing elements in real time embedded client server systems. In this paper we propose an improvement on COWLS algorithm to take into account preference and peak power consumption information. © 2007.

关键词： Embedded systems

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Bridging gap between simulation and spreadsheet study

Bridging gap between simulation and spreadsheet study

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Antoine Perrin Frank Ghenassia STMicroelectronics Grenoble France

system architects working on SoC design have traditionally been hampered by the lack of a cohesive methodology for architecture evaluation and co-verification of hardware and software. This paper focuses on a comprehensive analysis framework providing platform assembly facilities, system analysis tools, enhanced traffic model and systemC TLM IP. This framework has been intensively used to design and analyze complex SOC Interconnect based on STBus protocol such as the one of 71xx families. By hiding the complexity of a simulation and filling the gap towards spreadsheet study and costly On-Chip analysis using traffic model, architects benefit from an easy access to an efficient simulation for performance evaluation.

关键词： system-on-a-chip Analytical models Computer architecture Generators Real time systems Bridges Filling

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HW/SW co-design for Esterel processing

HW/SW co-design for Esterel processing

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Sascha Gädtke Claus Traulsen Reinhard von Hanxleden Real-Time and Embedded Systems Group Department of Computer Science Christian-Albrechts-Universität Kiel Kiel Germany

We present a co-synthesis approach that accelerates reactive software processing by moving the calculation of complex expressions into external combinational hardware. The starting point is a system model written in the synchronous language Esterel, which can be mapped to both hardware and software. Our approach performs the partitioning at the source-code level and preserves the original, strictly synchronous semantics. It is thus platform-independent and allows to use standard simulation and synthesis tools. Furthermore, the source-level partitioning approach presented here should be applicable to non-reactive processing platforms as well. However, the challenge is to partition the program without changing its meaning under any circumstances. In particular, signal scopes and interpartition signal dependencies must be maintained, which rules out a naïve top-level partitioning. We have implemented the co-synthesis approach based on the Columbia Esterel Compiler and have validated it on the Kiel Esterel Processor. As the experimental results confirm, this can significantly reduce execution times and energy consumption per reaction, with minimal additional hardware requirements.

关键词： hardware software Registers Benchmark testing Random access memory Semantics Field programmable gate arrays

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Combined approach to system level performance analysis of embedded systems

Combined approach to system level performance analysis of em...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Simon Künzli Arne Hamann Rolf Ernst Lothar Thiele Technologies Group Switzerland Technical University of Braunschweig Germany ETH Zürich Switzerland

Compositional approaches to system-level performance analysis have shown great flexibility and scalability in the design of heterogeneous systems. These approaches often assume certain system architectures and application domains, and are thus tailored to give tight analysis results for specific systems. We consider two different compositional analysis methods. Both methods have their particular strengths for different architectures and applications. In this paper, we aim to enhance the analysis capabilities for these techniques. A method for event model conversion allows us a seamless integration of the two methods. Finally, we present a detailed case study to show the applicability and benefits of the enhanced performance analysis technique.

关键词： Analytical models Performance analysis Jitter Approximation methods Computational modeling Timing Embedded systems

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HySim: A fast simulation framework for embedded software development

HySim: A fast simulation framework for embedded software dev...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Stefan Kraemer Lei Gao Jan Weinstock Rainer Leupers Gerd Ascheid Heinrich Meyr Institute for Integrated Signal Processing Systems RWTH Aachen University Germany

Instruction Set Simulation (ISS) is widely used in system evaluation and software development for embedded processors. Despite the significant advancements in the ISS technology, it still suffers from low simulation speed compared to real hardware. Especially for embedded software developers simulation speed close to real time is important in order to efficiently develop complex software. In this paper a novel, retargetable, hybrid simulation framework (HySim) is presented which allows switching between native code execution and ISS-based simulation. To reach a certain state of an application as fast as possible, all platform-independent parts of the application are directly executed on the host, while the platform dependent code executes on the ISS. During the native code execution a performance estimation is conducted. A case study shows that speed-ups ranging from 7× to 72× can be achieved without compromising debugging accuracy. The performance estimation during native code execution shows an average error of 9.5%.

关键词： Instruments Aerospace electronics Switches Estimation Coprocessors software Libraries

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Pointer re-coding for creating definitive MPSoC models

Pointer re-coding for creating definitive MPSoC models

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Pramod Chandraiah Rainer Dömer Center of Embedded Computer Systems University of California Irvine USA

Today's MPSoC synthesis and exploration design flows start from an abstract input specification model captured in a system level design language. Usually this model is created from a C reference code by encapsulating the computation and the communication using behaviors and channels. However, often pointers in the reference code hamper the necessary analysis and transformations. In this paper, we present an automated approach to re-code and eliminate pointers. By re-coding the pointer accesses to the actual variables, MPSoC models with definitive computational blocks that communicate using explicit channels become possible. Our pointer re-coding approach not only increases synthesizeabil-ity, analyzeability and verifiability by system tools, but also helps the designer in program comprehension. Our experiments show that this approach is not only feasible, but also effective in creating better models of real-life applications in shorter time.

关键词： Arrays Algorithm design and analysis Indexes Computational modeling Encoding Syntactics system-on-a-chip

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A smart random code injection to mask power analysis based side channel attacks

A smart random code injection to mask power analysis based s...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Jude Angelo Ambrose Roshan G. Ragel Sri Parameswaran University of New South Wales Sydney Australia

One of the security issues in embedded system is the ability of an adversary to perform side channel attacks. Power analysis attacks are often very successful, where the power sequence dissipated by the system is observed and analyzed to predict secret keys. In this paper we show a processor architecture, which automatically detects the execution of the most common encryption algorithms, starts to scramble the power waveform by adding randomly placed instructions with random register accesses, and stops injecting instructions when it is safe to do so. Our technique prevents both Simple Power Analysis (SPA) and Differential Power Analysis (DPA). This approach has less overheads compared to previous solutions and avoids software instrumentation, allowing programmers with no special knowledge to use the system. Our processor model costs an additional area of 1.2%, and an average of 25% in runtime and 28.5% in energy over heads for industry standard cryptographic algorithms.

关键词： Runtime Encryption Registers hardware Indexes Benchmark testing

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