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international conference on hardware/software codesign and system synthesis (CODES)

作者： James A. Boyle Mark Plagge Suma G. Cardwell Frances S. Chanc Andreas Gerstlauer The University of Texas at Austin Texas USA Sandia National Laboratories New Mexico USA

ISBN: (数字)9798350356397

ISBN: (纸本)9798350356403

Neuromorphic computing uses brain-inspired concepts to accelerate and efficiently execute a wide range of applications, such as mimicking biological circuits, solving NPhard optimization problems and accelerating machine learning at the edge. In particular, neuromorphic architectures to efficiently execute Spiking Neural Networks (SNNs) have gained popularity. SNNs extend artificial neural networks (ANNs) by encoding information in time as either rates or delays between spiking events, shared between neurons via their weighted connections. SNN-based platforms are event-driven, resulting in naturally sparse, noise-tolerant and power-efficient computation. In this tutorial, we present the state-of-the-art in scalable digital and analog spiking neuromorphic system architectures, and discuss current research trends within the neuromorphic architecture field at the system level. We further introduce our SANA-FE tool for Simulation of Advanced Neuromorphic Architectures for Fast Exploration, which has been developed as part of a collaboration between the University of Texas at Austin and Sandia National Laboratories. SANA-FE allows for modeling and performance-power prediction of different spiking hardware architectures executing SNN applications to support rapid, early system-level design-space exploration, hardware-aware application development and system architecture co-design. The tutorial includes a hands-on component in which SANA-FE’s capabilities are demonstrated and used to perform system design and application mapping case studies.

关键词： Neuromorphic engineering Neurons systems architecture Computer architecture Tutorials Spiking neural networks Predictive models Market research system analysis and design Optimization

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Special Session: Machine Learning for Embedded system Design

Special Session: Machine Learning for Embedded System Design

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Erika S. Alcorta Andreas Gerstlauer Chenhui Deng Qi Sun Zhiru Zhang Ceyu Xu Lisa Wu Wills Daniela Sánchez Lopera Wolfgang Ecker Siddharth Garg Jiang Hu The University of Texas at Austin Austin TX USA Cornell University Ithaca NY USA Duke University Durham NC USA Infineon Technologies AG Technical University of Munich Munich Germany New York University New York NY USA Texas A&M University College Station TX USA

Embedded systems are becoming increasingly complex, which has led to a productivity crisis in their design and verification. Although conventional design automation coupled with IP and platform reuse techniques have led to leaps in design productivity improvement, they face fundamental limits given that most design optimization and verification problems remain NP-hard and that reuse of pre-designed IP blocks and platforms inherently limits flexibility and optimality. At the same time, machine learning (ML) has recently made unprecedented advances and created phenomenal impact in various computing applications. In particular, application of ML techniques as a way to extract knowledge and learn from existing design, optimization and verification data has recently seen a lot of excitement and promise at lower physical and integrated circuit levels of abstraction. Using ML has the potential to similarly close the complexity gap in embedded system design, but corresponding ML-based approaches for embedded system optimization and verification at higher levels of abstraction are still at their infancy. This paper presents the current state of the art, along with opportunities and open challenges, in the application of ML methods for embedded system design and optimization. We discuss design and optimization at different levels of abstraction ranging from system-level modeling and optimization and high-level synthesis to RTL and micro-architecture design, bringing together perspectives from different communities in both academia and industry.

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An MLIR-based Compiler Flow for system-Level Design and hardware Acceleration 22

An MLIR-based Compiler Flow for System-Level Design and Hard...

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IEEE/acm 41st international conference on Computer Aided-Design (ICCAD)

作者： Agostini, Nicolas Bohm Curzel, Serena Amatya, Vinay Tan, Cheng Minutoli, Marco Castellana, Vito Giovanni Manzano, Joseph Kaeli, David Tumeo, Antonino PNNL Richland WA 99354 USA Politecn Milan Milan Italy Northeastern Univ Boston MA USA

ISBN: (纸本)9781450392174

The generation of custom hardware accelerators for applications implemented within high-level productive programming frameworks requires considerable manual effort. To automate this process, we introduce SODA-OPT, a compiler tool that extends the MLIR infrastructure. SODA-OPT automatically searches, outlines, tiles, and pre-optimizes relevant code regions to generate high-quality accelerators through high-level synthesis. SODA-OPT can support any high-level programming framework and domain-specific language that interface with the MLIR infrastructure. By leveraging MLIR, SODA-OPT solves compiler optimization problems with specialized abstractions. Backend synthesis tools connect to SODA-OPT through progressive intermediate representation lowerings. SODA-OPT interfaces to a design space exploration engine to identify the combination of compiler optimization passes and options that provides high-performance generated designs for different backends and targets. We demonstrate the practical applicability of the compilation flow by exploring the automatic generation of accelerators for deep neural networks operators outlined at arbitrary granularity and by combining outlining with tiling on large convolution layers. Experimental results with kernels from the PolyBench benchmark show that our high-level optimizations improve execution delays of synthesized accelerators up to 60x. We also show that for the selected kernels, our solution outperforms the current of state-of-the art in more than 70% of the benchmarks and provides better average speedup in 55% of them. SODA-OPT is an open source project available at https://***/sodalite/soda-opt.

关键词： MLIR High-Level Optimizations HLS Compilers

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Proceedings - 2022 IET international conference on Engineering Technologies and Applications, IET-ICETA 2022

Proceedings - 2022 IET International Conference on Engineeri...

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2022 IET international conference on Engineering Technologies and Applications, IET-ICETA 2022

ISBN: (纸本)9781665491389

The proceedings contain 146 papers. The topics discussed include: a research on smart machine tool’s processing parameter governed with monitored vibration data;movable wireless charging system for multiple electric vehicles;delay-based TCP with pacing and ECN for solving incast problem in data center networks;wireless human recognition design in indoor environment;high capacity information hiding method based on interpolation and ones’ complement;building wireless observation network to track biological clustering;a face mask detection system based on high level synthesis and hardware software codesign;soft sensing measurement of dissolved ammonia nitrogen in tank-based eel aquaculture systems utilizing deep learning;pose measurement of machine tool using inertial sensors;and lightweight architecture for face recognition system.

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A Podcast Creation Platform to Support News Corporations: Results from UX Evaluation 22

A Podcast Creation Platform to Support News Corporations: Re...

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acm international conference on Interactive Media Experiences (IMX)

作者： Almeida, Pedro Beca, Pedro Silva, Telmo Afonso, Marcelo Covalenco, Iulia Nicolau, Carolina Univ Aveiro Digimedia Aveiro Portugal

ISBN: (纸本)9781450392129

Podcasts as a media format have been increasing popular in recent years. The ease of access to this format have contributed for its success story. However, the creation of Podcasts requires specifc hardware and software for recording and editing it. Some platforms have emerged with the proposal to ease this creation process, namely by introducing Text-to-Speech (TTS) technologies removing the need for capturing and editing voice, reducing the efort necessary for producing this format, yet no platform allows the use of TTS in Portuguese of Portugal while retaining the scope of "podcast creation platform". Taking these limitations in mind we present the proposal of an all-in-one Podcast Creation platform with the availability of TTS Technology in Portuguese of Portugal. The paper describes the usability testing (UX) of the platform using 3 methodologies being: Self-Assessment Manikin (SAM), system Usability Scale (SUS) and Attrakdif. with promising results regarding its usability and desirability.

关键词： Text-To-Speech Content Creation Content Creation Platforms Digital Media Media Formats Speech synthesis

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Quantum hardware Roofline: Evaluating the Impact of Gate Expressivity on Quantum Processor Design

Quantum Hardware Roofline: Evaluating the Impact of Gate Exp...

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Quantum Computing and Engineering (QCE), IEEE international conference on

作者： Justin Kalloor Mathias Weiden Ed Younis John Kubiatowicz Bert De Jong Costin Iancu Department of Electrical Engineering and Computer Science University of California Berkeley Computational Research Division Lawrence Berkeley National Laboratory

ISBN: (数字)9798331541378

ISBN: (纸本)9798331541385

The design space of current quantum computers is expansive, with no obvious winning solution, leaving practitioners with a crucial question: “What is the optimal system configuration to run an algorithm?” This paper explores hardware design trade-offs across NISQ systems to better guide algorithm and hardware development. Algorithmic workloads and fidelity models drive the evaluation to appropriately capture architectural features such as gate expressivity, fidelity, and crosstalk. As a result of our analysis, we extend the criteria for gate design and selection from only maximizing average fidelity to a more comprehensive approach that additionally considers expressivity with respect to algorithm structures. A custom synthesis-driven compilation workflow that produces minimal circuit representations for a given system configuration drives our methodology and allows us to analyze any gate set effectively. In this work, we focus on native entangling gates (CNOT, ECR, CZ, ZZ, XX, Sycamore, √iSWAP), proposed gates (B Gate, 4 √CNOT, - 8 √CNOT), as well as parameterized gates (FSim, XY). By providing a method to evaluate the suitability of algorithms for hardware platforms, this work emphasizes the importance of hardware-software codesign for quantum computing.

关键词： Quantum system Quantum computing Computational modeling Logic gates Parallel processing Benchmark testing hardware Circuit synthesis Topology Integrated circuit modeling

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The 2019 Embedded systems Week (ESWEEK)

IEEE DESIGN & TEST

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IEEE DESIGN & TEST 2020年第1期37卷 100-101页

作者： Eles, Petru Mitra, Tulika Linkoping Univ Linkoping Sweden Natl Univ Singapore Dept Comp Sci Singapore 117417 Singapore

Embedded systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for smart, intelligent, and connected computing systems. By bringing together three leading conferences [the international conference on Compilers, Architecture, and synthesis for Embedded systems (CASES), the international conference on hardware/software codesign and system synthesis (CODES+ISSS), and the international conference on Embedded software (EMSOFT)], a special Internet of Medical Things (IoMT) day, a symposium [the international Symposium on Networks-on-Chip (NOCS)], and hottopic workshops and tutorials, ESWEEK presents the attendees with a wide range of topics unveiling state-of-the-art embedded software, embedded architectures, and embedded system designs.

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HiveMind: A hardware-software system Stack for Serverless Edge Swarms 22

HiveMind: A Hardware-Software System Stack for Serverless Ed...

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49th IEEE/acm Annual international Symposium on Computer Architecture (ISCA)

作者： Patterson, Liam Pigorovsky, David Dempsey, Brian Lazarev, Nikita Shah, Aditya Steinhoff, Clara Bruno, Ariana Hu, Justin Delimitrou, Christina Cornell Univ Ithaca NY 14850 USA

ISBN: (纸本)9781450386104

Swarms of autonomous devices are increasing in ubiquity and size, making the need for rethinking their hardware-software system stack critical. We present HiveMind, the first swarm coordination platform that enables programmable execution of complex task workflows between cloud and edge resources in a performant and scalable manner. HiveMind is a software-hardware platform that includes a domain-specific language to simplify programmability of cloud-edge applications, a program synthesis tool to automatically explore task placement strategies, a centralized controller that leverages serverless computing to elastically scale cloud resources, and a reconfigurable hardware acceleration fabric for network and remote memory accesses. We design and build the full end-to-end HiveMind system on two real edge swarms comprised of drones and robotic cars. We quantify the opportunities and challenges serverless introduces to edge applications, as well as the trade-offs between centralized and distributed coordination. We show that HiveMind achieves significantly better performance predictability and battery efficiency compared to existing centralized and decentralized platforms, while also incurring lower network traffic. Using both real systems and a validated simulator we show that HiveMind can scale to thousands of edge devices without sacrificing performance or efficiency, demonstrating that centralized platforms can be both scalable and performant.

关键词： serverless edge swarms IoT cloud computing hardware acceleration domain specific language

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Higher-order hardware: Implementation and Evaluation of the Cephalopode Graph Reduction Processor

Higher-order Hardware: Implementation and Evaluation of the ...

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： Jeremy Pope Carl-Johan H. Seger Henrik Valter Department of CSE Chalmers University of Technology Gothenburg Sweden

ISBN: (数字)9798350378023

ISBN: (纸本)9798350378030

A major challenge with the practical deployment of Internet-of-Things (IoTs) is how to develop the high-quality code needed in order to produce robust and secure IoT devices. In other domains, high-level programming languages have shown to be efficient vehicles towards this. However, the very limited compute power provided by IoT devices have made it difficult to apply the same approach to IoT devices. The Cephalopode processor is an attempt at implementing a low power hardware device directly aimed at running a high-level functional language. By integrating many resource-heavy tasks like garbage collection and arbitrary precision arithmetic into dedicated hardware, the Cephalopode processor explores the hypothesis that high-level functional languages can be used even for low-power IoT devices. This paper presents the implementation and evaluation of the Cephalopode processor. We discuss the approach taken, the compiler and the architecture of the processor. We also describe the design process and design considerations. After implementation and synthesis we compare the processor to a conventional RISC-V processor running a functional language software environment. We also compare Cephalopode with running handwritten C code on the RISC-V processor.

关键词： Computer languages Codes Computer architecture Benchmark testing hardware software Internet of Things system analysis and design Arithmetic

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Invited Paper: Dilithium hardware-Accelerated Application Using OpenCL-Based High-Level synthesis

Invited Paper: Dilithium Hardware-Accelerated Application Us...

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IEEE international conference on Computer-Aided Design

作者： Islam Alexander El-Kady Apostolos P. Fournaris Vassilis Paliouras University of Patras Patras Greece Industrial Systems Institute/R.C. Athena Patras Greece

Post-quantum cryptography (PQC) has been gaining attention in the last few years due to the evolution of quantum computers and the need to replace traditional, quantum-attack-insecure cryptography schemes with quantum-attack-resistant schemes. Lattice-based cryptography (LBC) constitutes a highly promising post-quantum solution (Quantum Resistant), but implementations in software or hardware are challenging due to the use of operations based on large-size polynomials. LBC selected schemes for standardization by the National Institute of Standards and Technology (NIST), rely on matrix-to-matrix multiplications of high-order polynomials, having performance bottlenecks that are solved using the Number-Theoretic Transform (NTT). One of the NIST-selected schemes for digital signature (DS) is the CRYSTALS-Dilithium scheme, which uses $N=256$ degee polynomials. In this paper a hardware/software (HW/SW) co-design solution is proposed for all security levels of Dilithium, utilizing the OpenCL framework and Vitis High-Level synthesis (HLS) tool. In our work, the HW/SW co-design OpenCL mechanisms are analyzed extensively and communication overheads between the hardware kernel and an ARM processor are identified, while appropriate techniques are proposed in order to bypass the I/O time-bottleneck on a real-world application. The proposed implementation runs on the ARM Processing system (PS) of a Xilinx Multi-Processor system on Chip (MPSoC) system, utilizing the MPSoC FPGA Programmable Logic (PL) in order to accelerate the calculations relative to the heavy matrix-multiplication operation. Finally, the proposed HW/SW codesigned solution is realized as a real-world Linux-based Dilithium DS executable and manages to achieve realistic performance gain, in terms of time execution, versus a CPU-only execution ranging from 2-23% (depending on the utilized CPU Clock Frequency).

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