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A data protection unit for NoC-based architectures

A data protection unit for NoC-based architectures

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Leandro Fiorin Gianluca Palermo Slobodan Lukovic Cristina Silvano ALaRI-Faculty of Informatics University of Lugano Lugano Switzerland Dipartimento di Elettronica e Informazione Politecnico di Milano Milan Italy

Security is gaining increasing relevance in the development of embedded devices. Towards a secure system at each level of design, this paper addresses the security aspects related to Network-on-Chip (NoC) architectures, foreseen as the communication infrastructure of next-generation embedded devices. In the context of NoC-based Multiprocessor systems, we focus on the topic, not thoroughly faced yet, of data protection. We present the architecture of a Data Protection Unit (DPU) designed for implementation within the Network Interface (NI). The DPU supports the capability to check and limit the access rights (none, read, write or both) of processors requesting access to data locations in a shared memory - in particular distinguishing between the operating roles (supervisor or user) of processing elements. We explore different alternative implementations and demonstrate how the DPU unit does not affect the network latency if the memory request has the appropriate rights. In the experimental section we show synthesis results for different ASIC implementations of the Data Protection Unit.

关键词： Computer architecture Nickel Random access memory Permission Computer aided manufacturing system-on-a-chip

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Thread warping: A framework for dynamic synthesis of thread accelerators

Thread warping: A framework for dynamic synthesis of thread ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Greg Stitt Frank Vahid Department of Electrical and Computer Engineering University of Florida USA Department of Computer Science and Engineering University of California Riverside USA Center of Embedded Computer Systems University of California Irvine USA

We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circuits on FPGAs (field-programmable gate arrays). Building on dynamic synthesis for single-processor single-thread systems, known as warp processing, thread warping improves performances of multiprocessor systems by speeding up individual threads and by allowing more threads to execute concurrently. Furthermore, thread warping maintains the important separation of function from architecture, enabling portability of applications to architectures with different quantities of microprocessors and FPGA-an advantage not shared by static compilation/synthesis approaches. We introduce a framework of architecture, CAD tools, and operating system that together support thread warping. We summarize experiments on an extensive architectural simulation framework we developed, showing application speedups of 4× to 502×, averaging 130× compared to a multiprocessor system having four ARM11 microprocessors, for eight benchmark applications. Even compared to a 64-processor system, thread warping achieves 11× speedup.

关键词： Instruction sets Field programmable gate arrays Design automation Synchronization Microprocessors system-on-a-chip

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Dynamic security domain scaling on symmetric multiprocessors for future high-end embedded systems

Dynamic security domain scaling on symmetric multiprocessors...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hiroaki Inoue Akihisa Ikeno Tsuyoshi Abe Junji Sakai Masato Edahiro Nihon Denki Kabushiki Kaisha Minato-ku Tokyo JP NEC Informatec Systems Ltd. Kawasaki Kanagawa Japan NEC Corporation System IP Core Research Laboratories Sagamihara Kanagawa Japan

We propose a method for dynamic security domain scaling on SMPs that offers both highly scalable performance and high security for future high-end embedded systems. Its most important feature is its highly efficient use of processor resources, accomplished by dynamically changing the number of processors within a security domain in response to application load requirements. Two new technologies make this scaling possible without any virtualization software: 1) self-transition management and 2) unified virtual address mapping. Evaluations show that this domain control provides highly scalable performance and incurs almost no performance overhead in security domains. The increase in binary code size is less than 40 KB, and the time required for individual state transitions is of a single-millisecond order. This scaling is the first in the world to make possible dynamic changing of the number of processors within a security domain on an ARM SMP.

关键词： Security Context Registers Embedded systems Switches Process control

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Introducing energy and area estimation in HW/SW design flow based on transaction level modeling

Introducing energy and area estimation in HW/SW design flow ...

引用

18th international conference on Microelectronics (ICM 2006)

作者： Cheema, Muhammad Omer Hammami, Omar ENSTA 32 Blvd Victor F-75739 Paris France

ISBN: (纸本)9781424407644

Transaction Level Modeling (TLM) facilitates the system designer in decision making at early phases of electronic product development. Executable specifications obtained from TLM models are used for the exploration of various architectural parameters and configurations possible for a system. However, traditional design flows based on TLM don't take into account the area and energy consumption of the system which are inevitably the most important constraints in modern embedded system designs. Traditionally, area and energy estimation is incorporated in system design at RTL (Register Transfer Level) which comes later in system design cycles and most of the crucial design decisions for the system has already been taken at that stage. In this paper, we propose a methodology to incorporate area and energy estimation in TLM based system modeling. This methodology allows a system designer take system level design decisions in very early stages of system design hence avoiding redesign efforts and performance bottlenecks in advanced stages of a project. Results obtained by applying our methodology on an image processing application show the robustness of our approach.

关键词： hardware/software codesign behavioral synthesis transaction level modeling area and energy estimation

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Temperature-aware processor frequency assignment for MPSoCs using convex optimization

Temperature-aware processor frequency assignment for MPSoCs ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Srinivasan Murali Almir Mutapcic David Atienza Rajesh Gupta Stephen Boyd Giovanni De Micheli LSI EPF Lausanne Switzerland Department of Electrical Engineering University of Stanford USA DACYA Complutense University of Madrid Spain Department of Computer Science and Engineering University of California San Diego USA

The increasing processing capability of Multi-Processor systems-on-Chips (MPSoCs) is leading to an increase in chip power dissipation, which in turn leads to significant increase in chip temperature. An important challenge facing the MPSoC designers is to achieve the highest performance system operation that satisfies the temperature and power consumption constraints. The frequency of operation of the different processors and the application workload assignment play a critical role in determining the performance, power consumption and temperature profile of the MPSoC. In this paper, we propose novel convex optimization based methods that solve this important problem of temperature-aware processor frequency assignment, such that the total system performance is maximized and the temperature and power constraints are met. We perform experiments on several realistic SoC benchmarks using a cycle-accurate FPGA-based thermal emulation platform, which show that the systems designed using our methods meet the temperature and power consumption requirements at all time instances, while achieving maximum performance.

关键词： Mathematical model Optimization Power demand Steady-state Time frequency analysis Thermal conductivity system-on-a-chip

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A code-generator generator for Multi-Output Instructions

A code-generator generator for Multi-Output Instructions

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hanno Scharwaechter Rainer Leupers Gerd Ascheid Heinrich Meyr Jonghee M. Youn Yunheung Paek Integrated Signal Processing Systems RWTH Aachen University Germany Software Optimization & Restructuring Research Group Seoul National University South Korea

We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very common in the area of Application Specific Instruction Set Processors (ASIPs) and Digital Signal Processors (DSPs) which are frequently used in system-on-Chips as programmable cores. In order to provide high-level programmability, and consequently guarantee widespread acceptance, sophisticated compiler support for these programmable cores is of high importance. Since it is not possible to model MultiOutput Instructions as trees in the compiler's Intermediate Representation (IR), traditional approaches for code selection are not sufficient. Extending traditional code-generation approaches for MOI-selection is essentially a graph covering problem, which is known to be NP-complete. We present a new heuristic algorithm incorporated in a retargetable code-generator generator capable of exploiting arbitrary inherently parallel MOIs. We prove the concept by integrating the tool into the LCC compiler which has been targeted towards different Instruction Set Architectures based on the MIPS architecture. Several network applications as well as some DSP benchmarks were compiled and evaluated to obtain results.

关键词： Grammar Program processors Generators Assembly Pattern matching Protocols Encryption

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Ensuring secure program execution in multiprocessor embedded systems: A case study

Ensuring secure program execution in multiprocessor embedded...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Krutartha Patel Sri Parameswaran Seng Lin Shee School of Computer Science and Engineering University of New South Wales Sydney Australia

Multiprocessor SoCs are increasingly deployed in embedded systems with little or no security features built in. Code Injection attacks are one of the most commonly encountered security threats. Most solutions to this problem in the single processor domain are purely software based and have high overheads. A few hardware solutions have been provided for the single processor case, which significantly reduce overheads. In this paper, for the first time, we propose a methodology addressing code injection attacks in a multiprocessor domain. A dedicated security (monitor) processor is used to oversee the application at runtime. Each processor communicates with the monitor processor through a FIFO queue, and is continuously checked. Static analysis of program map and timing profile are used to obtain program information at compile time, which is utilized by the monitor processor at runtime. This information is encrypted using a secure key and stored in the monitor processor. A copy of this secure key is built into the processor's hardware and is used for decryption by the monitor processor. Each basic block of the program is also instrumented with security information that uniquely identifies itself at runtime. The information from static analysis thus allows the monitor processor to supervise the proceedings on each processor at runtime. Our approach uses a combination of hardware and software techniques to keep overheads to a minimum. We implemented our methodology on a commercial extensible processor (Xtensa LX). Our approach successfully detects the execution of injected code when tested on a JPEG multiprocessor benchmark. The results show a small increase of 6.6% in application processors' runtime (clock cycle count) and 35.2% in code size for the JPEG encoder benchmark.

关键词： Security Runtime Monitoring hardware Benchmark testing Transform coding software

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A computational reflection mechanism to support platform debugging in systemC

A computational reflection mechanism to support platform deb...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Bruno Albertini Sandro Rigo Guido Araujo Cristiano Araujo Edna Barros Williams Azevedo Institute of Computing State University of Campinas-UNICAMP Campinas Brazil Informatics Center UFPE Recife Brazil

system-level and Platform-based design, along with Transaction Level modeling (TLM) techniques and languages like systemC, appeared as a response to the ever increasing complexity of electronics systems design, where complex SoCs composed of several modules integrated on the same chip have become very common. In this scenario, the exploration and verification of several architecture models early in the design flow has played an important role. This paper proposes a mechanism that relies on computational reflection to enable designers to interact, on the fly, with platform simulation models written in systemC TLM. This allows them to monitor and change signals or even IP internal register values, thus injecting specific stimuli that guide the simulation flow through corner cases during platform debugging, which are usually hard to handle by standard techniques, thus improving functional coverage. The key advantages of our approach are that we do not require code instrumentation from the IP designer, do not need a specialized systemC library, and not even need the IP source code to be able to inspect its contents. The reflection mechanism was implemented using a C++ reflection library and integrated into a platform modeling framework. We evaluate our technique through some platform case studies.

关键词： IP networks Libraries Registers Debugging Dictionaries Clocks hardware

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Hierarchical coarse-grained stream compilation for software defined radio

Hierarchical coarse-grained stream compilation for software ...

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CASES'07: 2007 international conference on Compilers, Architecture, and synthesis for Embedded systems

作者： Lin, Yuan Kudlur, Manjunath Mahlke, Scott Mudge, Trevor Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI United States

ISBN: (纸本)9781595938268

software Defined Radio (SDR) is an emerging embedded domain where the physical layer of wireless protocols is implemented in software rather than the traditional application specific hardware. The operation throughput requirements of current third-generation (3G) wireless protocols are an order of magnitude higher than the capabilities of modern DSP processors. Due to this steep performance requirement, heterogeneous multiprocessor system-on-chip designs have been proposed to support SDR. Given the difficulty in compiling traditional digital signal processors, these new multiprocessor architectures provide even greater challenges for the programmers and compilers. In this paper, we utilize a hierarchical dataflow programming model, referred to as SPIR, that is designed for modeling SDR applications. We then present a coarse-grained data ow compilation strategy that assigns a SDR protocol's DSP kernels onto multiple processors, allocates memory buffers, and determines an execution schedule that meets a prescribed throughput. Unlike traditional approaches, coarse-grained compilation exploits task-level parallelism by scheduling concurrent DSP kernels instead of instructions. Because of the streaming nature of SDR protocols, we adapted an existing instruction-level software pipelining technique, modulo scheduling, for coarse-grained compilation. Our compilation methodology is able to generate parallel code that achieves near linear speedup on a SDR multiprocessor system. Copyright 2007 acm.

关键词： Hierarchical systems

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Predator: A predictable SDRAM memory controller

Predator: A predictable SDRAM memory controller

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Benny Akesson Kees Goossens Markus Ringhofer Technische Universiteit Eindhoven Netherlands NXP Semiconductors Research Delft University of Technnology Netherlands Graz University of Technology Austria

Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAMs, are shared between a multitude of IPs to satisfy these requirements at a low cost per bit. However, SDRAMs have highly variable access times that depend on previous requests. This makes it difficult to accurately and analytically determine latencies and the useful bandwidth at design time, and hence to guarantee that hard real-time requirements are met. The main contribution of this paper is a memory controller design that provides a guaranteed minimum bandwidth and a maximum latency bound to the IPs. This is accomplished using a novel two-step approach to predictable SDRAM sharing. First, we define memory access groups, corresponding to precomputed sequences of SDRAM commands, with known efficiency and latency. Second, a predictable arbiter is used to schedule these groups dynamically at run-time, such that an allocated bandwidth and a maximum latency bound is guaranteed to the IPs. The approach is general and covers all generations of SDRAM. We present a modular implementation of our memory controller that is efficiently integrated into the network interface of a network-on-chip. The area of the implementation is cheap, and scales linearly with the number of IPs. An instance with six ports runs at 200 MHz and requires 0.042 mm 2 in 0.13μm CMOS technology.

关键词： Bandwidth SDRAM Memory management Delay Switches Clocks system-on-a-chip

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