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Channel trees: Reducing latency by sharing time slots in time-multiplexed Networks on Chip

Channel trees: Reducing latency by sharing time slots in tim...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Andreas Hansson Martijn Coenen Kees Goossens Electronic Systems Group Eindhovan University of Technology Eindhoven Netherlands Corporate Research Department NXP Semiconductors Eindhoven Netherlands

Networks on Chip (NoC) have emerged as the design paradigm for scalable system on Chip communication infrastructure. A growing number of applications, often with firm (FRT) or soft real-time (SRT) requirements, are integrated on the same chip. To provide time-related guarantees, NoC resources are reserved, e.g. by non-work-conserving time-division multiplexing (TDM). Traditionally, reservations are made on a per-communication-channel basis, thus providing FRT guarantees to individual channels. For SRT applications, this strategy is overly restrictive, as slack bandwidth is not used to improve performance. In this paper we introduce the concept of channel trees, where time slots are reserved for sets of communication channels. By employing work-conserving arbitration within a tree, we exploit the inherent single-threaded behaviour of the resource at the root of the tree, resulting in a drastic reduction in both average-case latency and TDM-table size. We show how channel trees enable us to halve the latter in a car entertainment SoC, and reduce the average latency by as much as much as 52% in a mobile phone SoC. By applying channel trees to an H264 decoder SoC, we increase processor utilisation by 25%.

关键词： Time division multiplexing system-on-a-chip Bandwidth Nickel Resource management Intellectual property SDRAM

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Compiling code accelerators for FPGAs

Compiling code accelerators for FPGAs

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Walid A. Najjar Computer Science & Engineering University of California Riverside Riverside CA USA

This tutorial addresses the challenges and opportunities presented by compiled FPGA-based code accelerators. In recent years we have witnessed a fast growth of both size and speed of FPGAs. These had been initially designed and marketed as convenient devices for “glue logic.” Later, they became used as fast prototyping platforms. As their size and speed grew, they have been used for the short time to market they can afford. Lately, their size and speed have made them attractive as code accelerator. While the clock speed achievable on a typical FPGA design is about an order of magnitude lower than that on a typical CPU, their advantage comes from two sources: (1) Large degree of instruction and loop level parallelism. Parallel loops can typically be unrolled by factors ranging in the 100s. (2) Increased efficiency of hardware execution. The streaming of the data through a dedicated circuit eliminates a large number of support operations such as data fetch, address calculations, index management, loop control, etc. The combined higher efficiency and parallelism of hardware execution on FPGAs has been shown to result in speedups ranging from the 10s to the 1,000s over traditional processor on frequently executed code segments. However, the main obstacle to wider acceptance of this technology is programmability. FPGAs are typically programmed using hardware Description Languages (HDLs), which poses two problems: Traditional application developers are typically not HDL designers, and HDLs are not well suited for algorithm implementation. Furthermore, the FPGA is an amorphous mass of logic on which the compiler must create a data-path and schedule the computation. Such a task requires the harnessing of technologies developed for parallelizing compilers as well as those developed for high-level synthesis. The main challenge that faces HLL to HDL translation is the paradigm shift from the stored program model to a value-based, data-driven execution - that is, from temporal

关键词： Field programmable gate arrays hardware design languages Parallel processing hardware Tutorials Computer architecture Clocks

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Compile-time decided instruction cache locking using worst-case execution paths

Compile-time decided instruction cache locking using worst-c...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Heiko Falk Sascha Plazar Henrik Theiling Computer Science 12 University of Dortmund Dortmund Germany AbsInt Angewandte Informatik GmbH Saarbrucken Germany

Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability is highly undesired for real-time systems. The Worst-Case Execution Time (WCET) of a software running on an embedded processor is one of the most important metrics during real-time system design. The WCET depends to a large extent on the total amount of time spent for memory accesses. In the presence of caches, WCET analysis must always assume a memory access to be a cache miss if it can not be guaranteed that it is a hit. Hence, WCETs for cached systems are imprecise due to the overestimation caused by the caches. Modern caches can be controlled by software. The software can load parts of its code or of its data into the cache and lock the cache afterwards. Cache locking prevents the cache's contents from being flushed by deactivating the replacement. A locked cache is highly predictable and leads to very precise WCET estimates, because the uncertainty caused by the replacement strategy is eliminated completely. This paper presents techniques exploring the lockdown of instruction caches at compile-time to minimize WCETs. In contrast to the current state of the art in the area of cache locking, our techniques explicitly take the worst-case execution path into account during each step of the optimization procedure. This way, we can make sure that always those parts of the code are locked in the I-cache that lead to the highest WCET reduction. The results demonstrate that WCET reductions from 54% up to 73% can be achieved with an acceptable amount of CPU seconds required for the optimization and WCET analyses themselves.

关键词： Benchmark testing Optimization Algorithm design and analysis Context software Transform coding Real time systems

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Three-dimensional multiprocessor system-on-chip thermal optimization

Three-dimensional multiprocessor system-on-chip thermal opti...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Chong Sun Li Shang Robert P. Dick ECE Department Queen''s University Kingston ONT Canada EECS Department Northwestern University Evanston IL USA

3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density of 3D MPSoCs increases with the number of active layers, resulting in high chip temperatures. This can reduce system reliability, reduce performance, and increase cooling cost. Thermal optimization for 3D MPSoCs imposes numerous challenges. It is difficult to manage assignment and scheduling of heterogeneous workloads to maintain thermal safety. In addition, the thermal characteristics of 3D MP-SoCs differ from those of 2D MPSoCs because each stacked layer has a different thermal resistance to the ambient and vertically-adjacent processors have strong temperature correlation. We propose a 3D MPSoC thermal optimization algorithm that conducts task assignment, scheduling, and voltage scaling. A power balancing algorithm is initially used to distribute tasks among cores and active layers. Detailed thermal analysis is used to guide a hotspot mitigation algorithm that incrementally reduces the peak MPSoC temperature by appropriately adjusting task execution times and voltage levels. The proposed algorithm considers leakage power consumption and adapts to inter-layer thermal heterogeneity. Performance evaluation on a set of multiprogrammed and multithreaded benchmarks indicates that the proposed techniques can optimize 3D MPSoC power consumption, power profile, and chip peak temperature.

关键词： Three dimensional displays Algorithm design and analysis Thermal analysis Optimization Program processors Power demand Heuristic algorithms

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hardware Estimation and synthesis for a codesign system

Hardware Estimation and Synthesis for a Codesign System

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international conference on Signal Processing, Communication and Networking (ICSCN)

作者： M. Sangeetha J. RajaPaul Perinbam Revathy College of Engineering Department of Electronics and Communication Engineering Anna University Guindy India Department of Electronics and Communication Engineering S. A. Engineering College Chennai India

A software model of hardware estimator is developed. The behavioral description is transformed into an intermediate format called control flow graph (CFG). The graph is partitioned into hardware and software. The unoptimized hardware in intermediate graph is estimated by transforming the graph into matrix format. The partitioned hardware of control flow graph is translated as behavioral network graph. The high level synthesis and logic synthesis are performed using the BNG with simple logical transformation. The final RTL obtained from the conventional synthesis method and BNG method for resource and timing constraint were presented. The cost estimation for the various control construction is being tabulated

关键词： hardware High level synthesis Logic Network synthesis Synthesizers Resource management Flow graphs Timing Delay Costs

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Automated refinement checking of concurrent systems

Automated refinement checking of concurrent systems

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IEEE international conference on Computer-Aided Design

作者： Sudipta Kundu Sorin Lerner Rajesh Gupta University of California San Diego La Jolla CA USA

Stepwise refinement is at the core of many approaches to synthesis and optimization of hardware and software systems. For instance, it can be used to build a synthesis approach for digital circuits from high level specifications. It can also be used for post-synthesis modification such as in engineering change orders (ECOs). Therefore, checking if a system, modeled as a set of concurrent processes, is a refinement of another is of tremendous value. In this paper, we focus on concurrent systems modeled as communicating sequential processes (CSP) and show their refinements can be validated using insights from translation validation, automated theorem proving and relational approaches to reasoning about programs. The novelty of our approach is that it handles infinite state spaces in a fully automated manner. We have implemented our refinement checking technique and have applied it to a variety of refinements. We present the details of our algorithm and experimental results. As an example, we were able to automatically check an infinite state space buffer refinement that cannot be checked by current state of the art tools such as FDR. We were also able to check the data part of an industrial case study on the EP2 system.

关键词： State-space methods hardware Refining Circuit synthesis Reasoning about programs Humans Manuals software systems Digital circuits Silicon

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CODES+ISSS 2005 - international conference on hardware/software codesign and system synthesis

CODES+ISSS 2005 - International Conference on Hardware/Softw...

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3rd IEEE/acm/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

ISBN: (纸本)1595931619

The proceedings contain 61 papers from the Codes+ISSS 2005 - international conference on hardware/software codesign and system synthesis. The topics discussed include: hardware and software architecture for the CELL processor;performance and power analysis of computer systems;the challenge of embedded system design;conflict analysis in multipurpose synthesis for optimized system integration;a cycle-accurate compilation algorithm for custom pipelines datapaths;highly flexible multi-mode system synthesis;implementation of dynamic streaming applications on heterogeneous multi-processor architectures;and increasing on-chip memory space utilization for embedded chip multiprocessors through data compression.

关键词： Computer software

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Promises and challenges of mobile embedded system: An industry perspective 06

Promises and challenges of mobile embedded system: An indust...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Woo, Nam-Sung Samsung Electronics

ISBN: (纸本)1595933700

Recent trends of IT industry include Mobile/Portable Solution, Integration and Faster Time-to-Market. These trends impose many interesting challenges to Embedded system development both in hardware and software. In this talk, we will first identify some of the challenges. Then, we will present both the current status and plans of Samsung Electronics (in particular, Samsung Semiconductor) to address and overcome the challenges. © Copyright 2006 acm.

关键词： Information technology

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A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH

A unified hardware/software runtime environment for FPGA-bas...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： So, Hayden Kwok-Hay Tkachenko, Artem Brodersen, Robert Department of Electrical Engineering and Computer Science University of California Berkeley

ISBN: (纸本)1595933700

This paper presents a hw/sw codesign methodology based on BORPH, an operating system designed for FPGA-based reconfigurable computers (RC's). By providing native kernel support for FPGA hardware, BORPH offers a homogeneous UNIX interface for both software and hardware processes. hardware processes inherit the same level of service from the kernel, such as file system support, as typical UNIX software processes. hardware and software components of a design therefore run as hardware and software processes within BORPH's run-time environment. The familiar and language independent UNIX kernel interface facilitates easy design reuse and rapid application development. Performance of our current implementation and our experience with developing a real-time wireless digital signal processing system based on BORPH will be presented. © Copyright 2006 acm.

关键词： Field programmable gate arrays (FPGA)

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Increasing hardware efficiency with multifunction loop accelerators

Increasing hardware efficiency with multifunction loop accel...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Fan, Kevin Kudlur, Manjunath Park, Hyunchul Mahlke, Scott Advanced Computer Architecture Laboratory University of Michigan Ann Arbor MI 48109

ISBN: (纸本)1595933700

To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop accelerators are traditionally designed in a single-function manner, wherein each loop nest is implemented as a dedicated hardware block. This paper focuses on hardware sharing across loop nests by creating multifunction loop accelerators, or accelerators capable of executing multiple algorithms. A compiler-based system for automatically synthesizing multifunction loop accelerator architectures from C code is presented. We compare the effectiveness of three architecture synthesis approaches with varying levels of complexity: sum of individual accelerators, union of individual accelerators, and joint accelerator synthesis. Experiments show that multifunction accelerators achieve substantial hardware savings over combinations of single-function designs. In addition, the union approach to multifunction synthesis is shown to be effective at creating low-cost hardware by exploiting hardware sharing, while remaining computationally tractable. © Copyright 2006 acm.

关键词： Computer hardware

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