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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Issenin, Ilya Dutt, Nikil University of California Irvine CA 92697

ISBN: (纸本)1595933700

The memory subsystem of a complex multiprocessor systems-on-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as of communication architecture, both affect the power efficiency of the design. In this paper we propose a novel approach that enables energy-aware co-synthesis of both memory and communication architecture for streaming applications. As opposed to earlier techniques, we employ a powerful compile-time analysis of memory access behavior that adds flexibility in selecting memory architectures. Additionally, we target TDMA bus-based communication architectures, which not only guarantee performance, but also greatly reduce the design time and allow us to find the energy optimal system configuration. We propose and compare three techniques: an optimal mixed ILP-based co-synthesis technique, a mixed ILP-based traditional two-step synthesis approach where memory and communication synthesis is performed sequentially, and a co-synthesis heuristic that synthesizes energy-efficient hierarchical bus-based communication architectures with guaranteed throughput. Our experimental results on a number of streaming applications show that both the traditional two-step synthesis approach and heuristic result in up to 50% worse power consumption in comparison with proposed co-synthesis approach. However, on some of the streaming benchmarks, our co-synthesis heuristic approach was able to find optimal or near-optimal results in a much shorter time than the MILP co-synthesis approach. © Copyright 2006 acm.

关键词： Multiprocessing systems

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Fuzzy decision making in embedded system design

Fuzzy decision making in embedded system design

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Di Nuovo, Alessandro G. Palesi, Maurizio Patti, Davide Ascia, Giuseppe Catania, Vincenzo Dipartimento di Ingegneria Informatica e Delle Telecomunicazioni Università Degli Studi di Catania Catania Italy DIIT Università di Catania

ISBN: (纸本)1595933700

The use of Application Specific Instruction-set Processors (ASIP) is a solution to the problem of increasing complexity in embedded systems design. One of the major challenges in ASIP design is Design Space Exploration (DSE), because of the heterogeneity of the objectives and parameters involved. Typically DSE is a multi-objective search problem, where performance, power, area, etc. are the different optimization criteria. The output of a DSE strategy is a set of candidate design solutions called a Pareto-optimal set. Choosing a solution for system implementation from the Pareto-optimal set can be a difficult task, generally because Pareto-optimal sets can be extremely large or even contain an infinite number of solutions. In this paper we propose a methodology to assist the decision-maker in analysis of the solutions to multi-objective problems. By means of fuzzy clustering techniques, it finds the reduced Pareto subset, which best represents all the Pareto solutions. This optimal subset will be used for further and more accurate (but slower) analysis. As a real application example we address the optimization of area, performance, and power of a VLIW-based embedded system. © Copyright 2006 acm.

关键词： Fuzzy systems

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hardware /software codesign of image processing applications using transaction level modeling

Hardware /software codesign of image processing applications...

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CAMPS 2006 - international Workshop on Computer Architecture for Machine Perception and Sensing

作者： Cheema, Muhammad Orner Hammami, Omar Lacassagne, Lionel Merigot, Alain ENSTA 32 Boulevard Victor 75739 Paris France IEF University of Paris Sud 91405 Orsay France

ISBN: (纸本)1424406862

Transaction Level Modeling (TLM) and component based software development approaches accelerate the process of an embedded system design and simulation and hence improve the overall productivity. On the other hand, system level design languages facilitate the fast hardware synthesis at behavioral level of abstraction. In this paper, we introduce an approach for hardware/software codesign of image processing application that uses TLM and component based software design approaches along with HW synthesis using systemC to accelerate system design and verification process. Our experiments performed over an image processing application shows the effectiveness of our methodology. © 2006 IEEE.

关键词： hardware-software codesign

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Multi-processor system design with ESPAM

Multi-processor system design with ESPAM

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Nikolov, Hristo Stefanov, Todor Deprettere, Ed Leiden Institute of Advanced Computer Science Leiden University Netherlands

ISBN: (纸本)1595933700

For modern embedded systems, the complexity of embedded applications has reached a point where the performance requirements of these applications can no longer be supported by embedded system architectures based on a single processor. Thus, the emerging embedded system-on-Chip platforms are increasingly becoming multiprocessor architectures. As a consequence, two major problems emerge, i.e., how to design and how to program such multiprocessor platforms in a systematic and automated way in order to reduce the design time and to satisfy the performance needs of applications executed on these platforms. Unfortunately, most of the current design methodologies and tools are based on Register Transfer Level (RTL) descriptions, mostly created by hand. Such methodologies are inadequate, because creating RTL descriptions of complex multiprocessor systems is error-prone and time *** an efficient solution to these two problems, in this paper we propose a methodology and techniques implemented in a tool called Espam for automated multiprocessor system design and implementation. Espam moves the design specification from RTL to a higher, so called system level of abstraction. We explain how starting from system level platform, application, and mapping specifications, a multiprocessor platform is synthesized and programmed in a systematic and automated way. Furthermore, we present some results obtained by applying our methodology and Espam tool to automatically generate multiprocessor systems that execute a real-life application, namely a Motion-JPEG encoder. © Copyright 2006 acm.

关键词： Multiprocessing systems

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Thermal-aware high-level synthesis based on network flow method

Thermal-aware high-level synthesis based on network flow met...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Lim, Pilok Kim, Taewhan School of Electrical Enginnering and Computer Science Seoul National University Seoul Korea Republic of

ISBN: (纸本)1595933700

Lowering down the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reliability, performance and leakage power of chip, and also increases the packaging cost. In this work, we address a new problem of thermal-aware module binding in high-level synthesis, in which the objective is to minimize the peak temperature of the chip. The two key contributions are (1) to solve the binding problem with the primary objective of minimizing the 'peak' switched capacitance of modules and the secondary objective of minimizing the 'total' switched capacitance of modules and (2) to control the switched capacitances with respect to the floorplan of modules in a way to minimize the 'peak' heat diffusion between modules. For (1), our proposed thermal-aware binding algorithm, called TA-b, formulates the thermal-aware binding problem into a problem of repeated utilization of network flow method, and solve it effectively. For (2), TA-b is extended, called TA-bf, to take into account a floorplan information, if exists, of modules to be practically effective. From experiments using a set of benchmarks, it is shown that TA-bf is able to use 10.1?C and 11.8?C lower peak temperature on the average, compared to that of the conventional low-power and thermalaware methods, which target to minimizing total switched capacitance only ([18]) and to minimizing peak switched capacitance only ([16]), respectively. © Copyright 2006 acm.

关键词： Microprocessor chips

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SHAPES: A tiled scalable software hardware architecture platform for embedded systems

SHAPES: A tiled scalable software hardware architecture plat...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Paolucci, Pier S. Jerraya, Ahmed A. Leupers, Rainer Thiele, Lothar Vicini, Piero ATMEL Roma INFN INFN Dip. Fisica Univ. Roma Italy TIMA INPG 46 Av. Félix Viallet 38031 Grenoble Cedex France Inst. for Integrated Signal Proc. Syst. Aachen Univ. of Technology Germany Zürich Switzerland INFN C/o Dip. Fisica Univ. Roma la Sapienza P.le Aldo Moro 5 00185 Roma Italy

ISBN: (纸本)1595933700

Nanoscale systems on chip will integrate billion-gate designs. The challenge is to find a scalable HW/SW design style for future CMOS technologies. Tiled architectures suggest a possible path: "small" processing tiles connected by "short wires". A typical SHAPES tile contains a VLIW floating-point DSP, a RISC, a DNP (Distributed Network Processor), distributed on chip memory, the POT (a set of Peripherals On Tile) plus an interface for DXM (Distributed External Memory). The SHAPES routing fabric connects on-chip and off-chip tiles, weaving a distributed packet switching network. 3D next-neighbours engineering methodologies is adopted for off-chip networking and maximum system density. The SW challenge is to provide a simple and efficient programming environment for tiled architectures. SHAPES will investigate a layered system software, which does not destroy algorithmic and distribution info provided by the programmer and is fully aware of the HW paradigm. For efficiency and QoS, the system SW manages intra-tile and inter-tile latencies, bandwidths, computing resources, using static and dynamic profiling. The SW accesses the on-chip and off-chip networks through a homogeneous interface. © Copyright 2006 acm.

关键词： Embedded systems

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system-level power-performance tradeoffs for reconfigurable computing

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2006年第7期14卷 730-739页

作者： Noguera, Juanjo Badia, Rosa M. Tech Univ Catalonia Comp Architecture Dept Barcelona 08034 Spain

In this paper, we propose a configuration-aware data-partitioning approach for reconfigurable computing, We show how the reconfiguration overhead impacts the data-partitioning process. Moreover, we explore the system-level power-performance tradeoffs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. For a certain group of streaming applications, we show that an efficient hardware/software partitioning algorithm is required when targeting low power. However, if the application objective is performance, then we propose the use of dynamically reconfigurable architectures. We propose a design methodology that adapts the architecture and algorithms to the application requirements. The methodology hag been proven to work on a real research platform based on Xilinx devices. Finally, we have applied our methodology, and algorithms to the case study of image sharpening, which is required nowadays in digital cameras and mobile phones.

关键词： hardware/software (HW/SW) codesign power-performance tradeoffs reconfigurable computing (RC)

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Creation and utilization of a virtual platform for embedded software optimization: An industrial case study

Creation and utilization of a virtual platform for embedded ...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Hong, Sungpack Yoo, Sungjoo Lee, Sheayun Lee, Sangwoo Nam, Hye Jeong Yoo, Bum-Seok Hwang, Jaehyung Song, Donghyun Kim, Janghwan Kim, Jeongeun Jin, Hoonsang Choi, Kyu-Myung Kong, Jeong-Taek Eo, Sookwan CAE Team System LSI Division Samsung Electronics CO. LTD. Flash Software Group Memory Division Samsung Electronics CO. LTD. Storage Team System LSI Division Samsung Electronics CO. LTD. HDD Development Group Storage Division Samsung Electronics CO. LTD. Software Laboratories Mobile SW Platform Samsung Electronics Co. Ltd.

ISBN: (纸本)1595933700

Virtual platform (ViP), or ESL (Electronic system Level) simulation model, is one of the most widely renowned system level design techniques. In this paper, we present a case study of creating and applying the ViP in the development of a new hard disk system called Hybrid-HDD that is one of the main features in the Windows VISTA (R). First, we summarize how we developed the ViP including the levels of timing accuracy of models, automatic generation of models from RTL code, external subsystem models, etc. Then, we explain how we exploited the ViP in software optimization. Compared with the conventional flow of software development, e.g. based on the real board, the ViP gives a better profiling capability thereby allowing designers to find more chances of code optimization. Based on the simulation and analysis with the ViP, the software optimization could improve system performance by more than 50%. However, in our case study, we found that the current ViP technique needs further improvements to become a true ESL design technique.

关键词： Embedded systems

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hardware estimation and synthesis for a codesign system

Hardware estimation and synthesis for a codesign system

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international conference on Signal Processing, Communications and Networks

作者： Sangeetha, M. Perinbam, J. RajaPaul Revathy Anna Univ Coll Engn Dept Elect & Commun Engn Madras 600025 Tamil Nadu India SA Engn Coll Dept Elect & Commun Engn Madras Tamil Nadu India

ISBN: (纸本)9781424409969

A software model of hardware estimator is developed. The behavioral description is transformed into an intermediate format called Control Flow Graph (CFG). The graph is partitioned into hardware and software. The unoptimized hardware in intermediate graph is estimated by transforming the graph into matrix format. The partitioned hardware of Control Flow Graph is translated as behavioral network graph. The High Level synthesis and Logic synthesis are performed using the BNG with simple logical transformation. The final RTL obtained from the conventional synthesis method and BNG method for resource and timing constraint were presented. The cost estimation for the various control construction is being tabulated.

关键词： Codes (symbols)

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Architectural support for safe software execution on embedded processors

Architectural support for safe software execution on embedde...

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CODES+ISSS 2006: 4th international conference on hardware software codesign and system synthesis

作者： Arora, Divya Raghunathan, Anand Ravi, Srivaths Jha, Niraj K. Dept. of Electrical Engineering Princeton University Princeton NJ 08544 NEC Laboratories America Princeton NJ 08540

ISBN: (纸本)1595933700

The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and more recently, system security. A major portion of known security attacks against software systems can be attributed to this shortcoming, including the well-known stack overflow, heap overflow, and format string attacks. Despite their limitations, the flexibility, performance, and ease of use of these languages have made them the choice of most embedded software developers. Researchers have proposed various techniques to enhance programs for memory safety;however, they are all subject to severe performance penalties, making their use impractical in most scenarios. In this paper, we present architectural enhancements to enable efficient, memory-safe execution of software on embedded processors. The key insight behind our approach is to extend embedded processors with hardware that significantly accelerates the execution of the additional computations involved in memory-safe execution. Specifically, we design custom instructions to perform various kinds of memory-safety checks and augment the instruction set of a state-of-the-art extensible processor (Xtensa from Tensilica, Inc.) to implement them. We demonstrate the application of the proposed architectural enhancements using CCured, an existing tool for type-safe retrofitting of C programs. The tool uses a type-inferencing engine that is built around strong type-safety theory and is provably safe. Simulations of memory-safe versions of popular embedded benchmarks on a cycle-accurate simulator modeling a typical embedded system configuration indicate an average performance improvement of 2.3x, and a maximum of 4.6x when using the proposed architecture. These enhancements entail minimal (less than 10%) hardware overhead to the base processor. Our approach is completely automated, and applicable to any C program, making it a promising and practi

关键词： Embedded systems

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