检索结果-内蒙古大学图书馆

2nd international conference on hardware/software codesign and systems synthesis

作者： Kim, Sungchan Ha, Soonhoi Seoul Natl Univ Dept Comp Sci & Engn Codesign & Parallel Proc Lab Seoul 151742 South Korea Samsung Elect Yongin 446711 Gyeonggi South Korea

Separation between computation and communication in system design allows system designers to explore the communication architecture independently after component selection and mapping decision is made. In this paper, we present an iterative two-step exploration methodology for bus-based on-chip communication architecture for multitask applications. We assume that the memory traces from the processing components are given. The proposed methodology uses a static performance estimation technique extended for multitask applications to reduce the design space quickly and drastically and applies a trace-driven simulation to the reduced set of design candidates for accurate performance estimation. For the case that local memory traffics as well as shared memory traffics are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. Experimental results show that the proposed methodology achieves significant performance gain by optimizing on-chip communication only, up to almost 100% compared with an initial single shared bus architecture, in both two real-life examples, a four-Channel digital video recorder and an equalizer for OFDM DVB-T receiver.

关键词： communication architecture design space exploration memory allocation multitask performance estimation

来源：评论

学校读者我要写书评

暂无评论

Platform-based behavior-level and system-level synthesis

Platform-based behavior-level and system-level synthesis

引用

IEEE international SOC conference

作者： Cong, Jason Fan, Yiping Han, Guoling Jiang, Wei Zhang, Zhiru Univ Calif Los Angeles Los Angeles CA 90001 USA

ISBN: (纸本)0780397819

With the rapid increase of complexity in system-on-a-Chip (SoC) design, the electronic design automation (EDA) community is moving from RTL (Register 'IYansfer Level) synthesis to behavioral-level and system-level synthesis. The needs of system-level verification and software/hardware codesign also prefer behavior-level executable specifications, such as C or systemC. In this paper we present the platform-based synthesis system, named xPilot, being developed at UCLA. The first objective of xPilot is to provide novel behavioral synthesis capability for automatically generating efficient RTL code from a C or systemC description for a given system platform and optimizing the logic, interconnects, performance, and power simultaneously. The second objective of xPilot is to provide a platform-based system-level synthesis capability, including both synthesis for application-specific configurable processors and heterogeneous multi-core systems. Preliminary experiments on FPGAs demonstrate the efficacy of our approach on a wide range of applications and its value in exploring various design tradeoffs.

关键词： Microprocessor chips

来源：评论

学校读者我要写书评

暂无评论

"It's a small world after all": NoC performance optimization via long-range link insertion

"It's a small world after all": NoC performance optimization...

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Ogras, Umit Y. Marculescu, Radu Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA

Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental, results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology.

关键词： design automation multiprocessor system-on-chip (MP-SoC) network-on-chip (NoC) performance analysis

来源：评论

学校读者我要写书评

暂无评论

Efficient exploration of bus-based system-on-chip architectures

引用

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2006年第7期14卷 681-692页

作者： Kim, Sungchan Ha, Soonhoi Seoul Natl Univ Dept Comp Sci & Engn Codesign & Parallel Proc Lab Seoul 151742 South Korea Samsung Elect Yongin 446711 Gyeonggi South Korea

关键词： communication architecture design space exploration memory allocation multitask performance estimation

来源：评论

学校读者我要写书评

暂无评论

hardware cryptography-embedded multimedia mobile system

Hardware cryptography-embedded multimedia mobile system

引用

10th World Multi-conference on systemics, Cybernetics and Informatics/12th international conference on Information systems Analysis and synthesis

作者： Fukase, Masa-aki Akaoka, Ryo Sato, Tomoaki Hirosaki Univ Dept Elect & Informat Syst Engn Hirosaki Aomori 0368561 Japan Hirosaki Univ Comp & Network Syst Ctr Hirosaki Aomori 0368561 Japan

ISBN: (纸本)9789806560680

Security aware multimedia mobility is crucial for the further progress of ubiquitous environment. Java has been promising in view of multimedia mobile features and easy treating, but this lacks simplicity in language processing and platform organization. This has resulted in the saturation of increasing the overall performance of ubiquitous network. On the other hand, user security has been really threatened due to diversified open access to the ubiquitous network, while the diversity from small devices to large machines brings about easy access anytime anywhere. Thus, ever growing ubiquitous community makes overall demands for security, speed, and power consciousness in processing large quantity of multimedia data. The key technology to answer these requirements will be a single VLSI (very large scale integration) chip processor and its software support system, We have exploited the H/S (hardware/software) codesign of a hardware cryptography-embedded multimedia mobile processor and its language processing. The processor named HCgorilla is a devised interpreter type Java CPU (central processing unit) with less power and higher throughput for multimedia cryptographic streaming. The language processing for HCgorilla includes a Java interface and parallelizing compilers. We describe in this article our recent results about the overall system of HCgorilla.

关键词： processor hardware cryptography multimedia mobile Java byte code

来源：评论

学校读者我要写书评

暂无评论

ISEGEN: An iterative improvement-based ISE generation technique for fast customization of processors

ISEGEN: An iterative improvement-based ISE generation techni...

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Biswas, Partha Banerjee, Sudarshan Dutt, Nikil D. Pozzi, Laura Ienne, Paolo MathWorks Inc Natick MA 01760 USA Univ Calif Irvine Donald Bren Sch Informat & Comp Sci Ctr Embedded Syst Irvine CA 92697 USA Univ Lugano Dept Informat CH-6900 Lugano Switzerland Ecole Polytech Fed Lausanne Sch Comp & Commun Sci Processor Architecture Lab CH-1015 Lausanne Switzerland

Customization of processor architectures through instruction set extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-quality ISE generation approach needs to obtain results close to those achieved by experienced designers, particularly for complex applications that exhibit regularity: expert designers are able to exploit manually such regularity in the data flow graphs to generate high-quality ISEs. In this paper, we present ISEGEN, an approach that identifies high-quality ISEs by iterative improvement following the basic principles of the well-known Kernighan-Lin min-cut heuristic. Experimental results on a number of MediaBench, EEMBC, and cryptographic applications show that our approach matches the quality of the optimal solution obtained by exhaustive search. We also show that our ISEGEN technique is on average 20 x faster than a genetic formulation that generates equivalent solutions. Furthermore, the ISEs identified by our technique exhibit 35% more speedup than the genetic solution on a large cryptographic application by effectively exploiting its regular structure.

关键词： application-specific processors hardware-software partitioning instruction set extensions

来源：评论

学校读者我要写书评

暂无评论

Energy minimization for real-time systems with (m, k)-guarantee

Energy minimization for real-time systems with (<i>m</i>, <i...

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Niu, Linwei Quan, Gang Univ S Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

Energy consumption and quality of service (QoS) are two primary concerns in the development of today's pervasive computing systems. While most of the current research in energy-aware real-time scheduling has been focused on hard real-time systems, a large number of practical applications and systems exhibit more soft real-time nature. In this paper, we study the problem of minimizing energy for soft real-time systems while providing a QoS guarantee. The QoS requirements are deterministically quantified with the (m, k)-constraints, which require that at least m out of any k consecutive jobs of a task meet their deadlines. In this paper, we propose a hybrid approach to achieve the dual goals of QoS guarantee and energy minimization. We first present the necessary and sufficient schedulability conditions for the static mandatory/optional workload partitioning. Then, we propose to dynamically vary the statically defined mandatory/optional partitions to accommodate dynamic run-time variations while minimizing the energy consumption. The experimental results demonstrate that our proposed techniques outperform previous work significantly in terms of both the energy savings and achieved QoS.

关键词： dynamic volage scaling (DVS) earliest deadline first (EDF) embedded system quality of service (QoS) real-time scheduling

来源：评论

学校读者我要写书评

暂无评论

Allocation cost minimization for periodic hard real-time tasks in energy-constrained DVS systems

Allocation cost minimization for periodic hard real-time tas...

引用

IEEE/acm international conference on Computer Aide Digest

作者： Chen, Jian-Jia Kuo, Tei-Wei Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei Taiwan

ISBN: (纸本)9781595933898

Energy-efficiency and power-awareness for electronic systems have been important design issues in hardware and software implementations. We consider the scheduling of periodic hard real-time tasks along with the allocation of processors under a given energy constraint. Each processor type could be associated with its allocation cost. The objective of this work is to minimize the entire allocation cost of processors so that the timing and energy constraints are both satisfied. We develop approximation algorithms for processor types with continuous processor speeds or discrete processor speeds. The capability of the proposed algorithms was evaluated by a series of experiments, and it was shown that the proposed algorithms always derived solutions with system costs close to those of optimal solutions in the experiments.

关键词： energy-aware systems task scheduling real-time systems task partitioning multiprocessor synthesis dynamic voltage scaling

来源：评论

学校读者我要写书评

暂无评论

Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation

引用

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) systemS 2006年第7期14卷 707-716页

作者： Zhu, Xinping Qin, Wei Malik, Sharad Northeastern Univ Dept Elect & Comp Engn Boston MA 02115 USA Boston Univ Dept Elect & Comp Engn Boston MA 02215 USA Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

In multiprocessor-based system-on-chips (SOCs), optimizing the communication architecture is often as important-as, if not more than, optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of computation architectures, the same is not true for the communication architectures. A major challenge in modeling the communication architecture is managing the concurrency at multiple levels: at the operation level, multiple communication operations may be active at any time;at the microarchitecture level, several microarchitectural components may be operating in parallel. Further, it is important to be able to clearly specify how the operation-level concurrency maps to the microarchitectural-level concurrency. This paper presents a modeling methodology and a retargetable simulation framework which fill this gap. This framework seeks to facilitate the design space exploration of the communication subsystem through a rigorous modeling approach based on a formal concurrency model, the operation state machine (OSM). Our OSM-based modeling methodology enables the entire system including both the computation and communication architectures to be modeled in a single OSM framework. This allows us to develop a tool set that can synthesize cycle-accurate system simulators for multiprocessing-element SOC prototypes. We show that, by simulation, critical system information such as timing and communication patterns can be obtained and evaluated. Consequently, system-level design choices regarding the communication architecture can be made with high confidence in early stages of design.

关键词： bus design exploration multiprocessor system on-chip communication architecture (OCA) packet-switching network retargetable simulation simulator synthesis

来源：评论

学校读者我要写书评

暂无评论

A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH

A unified hardware/software runtime environment for FPGA-bas...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Robert Brodersen Artem Tkachenko Hayden Kwok-Hay So Department of Electrical Engineering and Computer Science University of California Berkeley USA

This paper presents a hw/sw codesign methodology based on BORPH, an operating system designed for FPGA-based reconfigurable computers (RC's). By providing native kernel support for FPGA hardware, BORPH offers a homogeneous UNIX interface for both software and hardware processes. hardware processes inherit the same level of service from the kernel, such as file system support, as typical UNIX software processes. hardware and software components of a design therefore run as hardware and software processes within BORPH's run-time environment. The familiar and language independent UNIX kernel interface facilitates easy design reuse and rapid application development. Performance of our current implementation and our experience with developing a real-time wireless digital signal processing system based on BORPH will be presented.

关键词： hardware Runtime environment Operating systems Kernel Application software software design Field programmable gate arrays Computer interfaces software standards File systems

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：