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Resource virtualization in real-time CORBA middleware

Resource virtualization in real-time CORBA middleware

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Christopher D. Gill Department of Computer Science and Engineering Washington University Saint Louis MO USA

Middleware for parallel and distributed systems is designed to virtualize computation and communication resources so that a more abstract and consistent view of those resources is presented to the applications that use them. Providing such a consistent virtualization in distributed real-time and embedded systems becomes increasingly challenging due to application constraints such as timeliness and resource constraints such as CPU speed, power, memory, and bandwidth limitations, which also must be considered. This paper describes several examples of real-time CORBA middleware and examines how different constraints impact the way in which resources are virtualized in each case. Particular attention is paid to which details are hidden from users of the middleware, which details are exposed in the middleware's programming model, and how the hidden and exposed details interact to shape middleware design and implementation choices.

关键词： Resource virtualization Middleware Real time systems Application virtualization Distributed computing Concurrent computing Embedded system Programming profession Application software Computer architecture

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A run-time, feedback-based energy estimation model For embedded devices

A run-time, feedback-based energy estimation model For embed...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Chandra Krintz Selim Gurun Department of Computer Science University of California슠Santa Barbara Santa Barbara CA USA

We present an adaptive, feedback-based, energy estimation model for battery-powered embedded devices such as sensor network gate-ways and hand-held computers. Our technique maps hardware and software counters to energy consumption values using a set of first order, linear regression equations. Our system is novel in that it combines online and offline techniques to enable runtime power prediction. Our system employs an offline instantiated model that it continuously updates using feedback from a readily available battery monitor within the device. We empirically evaluate our model and detail its robustness, accuracy, and computational cost. We also analyze the stability of the model in the presence of feedback errors. We demonstrate that our approach can achieve an error rate of 1% (extant techniques: 2.6% to 4%) for computationally bound tasks and 6.6% (extant techniques: 11%) for communication bound tasks.

关键词： Runtime Power system modeling Feedback Computer networks Embedded computing Handheld computers hardware Counting circuits Energy consumption Linear regression

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Proceedings - Fourth acm & IEEE international conference on Formal Methods and Models for Co-Design MEMOCODE'06

Proceedings - Fourth ACM & IEEE International Conference on ...

引用

4th acm and IEEE international conference on Formal Methods and Models for Co-Design, MEMOCODE'06

ISBN: (纸本)1424404215

The proceedings contain 22 papers. The topics discussed include: games for formal design and verification of reactive systems;analyzing tabular requirements specifications using infinite state model checking;mixed symbolic representations for model checking software programs;low-power hardware synthesis from TRS-based specifications;scalable program analysis using boolean satisfiability;execution semantics and formalisms for multi-abstraction TLM assertions;a methodology for abstracting RTL designs into TL descriptions;using reo for formal specification and verification of system designs;specifying and proving properties of timed I/O automata in the TIOA toolkit;reliable design with multiple clock domains;the systemJ approach to system-level design;efficient code generation from synchronous programs;latency-insensitive design and central repetitive scheduling;and a scenario-aware data flow model for combined long-run average and worst-case performance analysis.

关键词： Formal methods

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Automatic selection of application-specific instruction-set extensions

Automatic selection of application-specific instruction-set ...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Carlo Galuzzi Elena Moscu Panainte Yana Yankova Koen Bertels Stamatis Vassiliadis Computer Engineering EEMCS Delft University of Technology Delft Netherlands

In this paper, we present a general and an efficient algorithm for automatic selection of new application-specific instructions under hardware resources constraints. The instruction selection is formulated as an ILP problem and efficient solvers can be used for finding the optimal solution. An important feature of our algorithm is that it is not restricted to basic-block level nor does it impose any limitation on the number of the newly added instructions or on the number of the inputs/outputs of these instructions. The presented results show that a significant overall application speedup is achieved even for large kernels (for ADPCM decoder the speedup ranges from times1.2 to times3.7) and that our algorithm compares well with other state-of-art algorithms for automatic instruction set extensions.

关键词： hardware MIMO Clustering algorithms Parallel processing Algorithm design and analysis Computer aided instruction Decoding Kernel Computational complexity Permission

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The pipeline decomposition tree:: an analysis tool for multiprocessor implementation of image processing applications

The pipeline decomposition tree:: an analysis tool for multi...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Shuvra S. Bhattacharyya Dong-Ik Ko Department of Electrical and Computer Engineering Institute for Advanced Computer Studies University of Maryland College Park USA

Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resource-related constraints. As this complexity increases, the application of single-chip multiprocessor technology is attractive. To address the challenges of mapping image processing applications onto embedded multiprocessor platforms, this paper presents a novel data structure called the pipeline decomposition tree (PDT), and an associated scheduling framework, which we refer to as PDT scheduling. PDT scheduling exploits both heterogeneous data parallelism and task-level parallelism, which are important considerations for scheduling image processing applications. This paper develops the PDT representation for system synthesis, and presents methods using the PDT to derive customized pipelined architectures that are streamlined for the given implementation constraints.

关键词： Pipelines Image analysis Image processing Processor scheduling Application software Embedded system Parallel processing Space exploration Multidimensional signal processing Embedded computing

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A methodology for design of application specific deadlock-free routing algorithms for NoC systems

A methodology for design of application specific deadlock-fr...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Vincenzo Catania Rickard Holsmark Shashi Kumar Maurizio Palesi Universita degli Studi di Catania Catania Sicilia IT Jönköping University Sweden University of Catania Italy

In this paper, we present a methodology to specialize the routing algorithm in routing table based NoC routers. It tries to maximize the communication performance while ensuring deadlock free routing for an application. We demonstrate through analysis that routing algorithms generated by our methodology have higher adaptiveness as compared to turn-model based deadlock free routing algorithms for a mesh topology NoC architecture. Performance evaluation is carried out by using a flit-accurate simulator on traffic scenarios generated by both synthetic and real applications. The routing algorithms generated by the proposed methodology achieve an improvement in delay close to 50% and 30% over deterministic XY routing algorithm and adaptive odd-even routing algorithm respectively.

关键词： Design methodology Algorithm design and analysis system recovery Routing Network-on-a-chip Network topology Communication networks Telecommunication traffic Communication switching Mesh generation

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Automatic phase detection for stochastic on-chip traffic generation

Automatic phase detection for stochastic on-chip traffic gen...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Tanguy Risset Antoine Fraboulet Antoine Scherrer LIP ENS de Lyon Lyon France CITI-INSA de Lyon Villeurbanne France

(NoC) prototyping is used for adapting NoC parameters to the application running on the chip. This prototyping is currently done using traffic generators which emulate the SoC components (IPs) behavior: processors, hardware accelerators, etc. Traffic generated by processor-like IPs is highly non-regular, it must be decomposed into program phases. We propose an original feature for NoC prototyping, inspired by techniques used in processor architecture performance evaluation: the automatic detection of traffic phases. Integrated in our NoC prototyping environment, this feature permits to have a completely automatic toolchain for the generation of stochastic traffic generators. We show that our traffic generators emulate precisely the behavior of processors and that our environment is a versatile tool for networks-on-chip prototyping. Simulations are performed in a systemC-based simulation environment with a mesh network-on-chip (DSPIN) and a processor running MP3 decoding applications.

关键词： Phase detection Stochastic processes Network-on-a-chip Traffic control Telecommunication traffic Prototypes system-on-a-chip hardware Computational modeling Space exploration

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Heterogeneous multiprocessor implementations for JPEG:: a case study

Heterogeneous multiprocessor implementations for JPEG:: a ca...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Andrea Erdos Sri Parameswaran Seng Lin Shee School of Computer Science and Engineering University of New South Wales Sydney Australia NICTA Sydney Australia

Heteregenous multiprocessor SoCs are becoming a reality, largely due to the abundance of transistors, intellectual property cores and powerful design tools. In this project, we explore the use of multiple cores to speed up the JPEG compression algorithm. We show two methods to parallelize this algorithm: one, a master-slave model; and two, a pipeline model. The systems were implemented using Tensilica's Xtensa LX processors with queues. We show that even with this relatively simple application, parallelization can be carried out with up to nine processors with utilization of between 50% to 80%. We obtained speed ups of up to 4.6X with a seven core system with an area increase of 3. 1X.

关键词： Australia Parallel processing Master-slave Pipelines Intellectual property Power system modeling Multicore processing Computer architecture Multiprocessing systems Instruction sets

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Increasing the throughput of an adaptive router in network-on-chip (NoC)

Increasing the throughput of an adaptive router in network-o...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Nader Bagherzadeh Seung Eun Lee Department of Electrical Engineering and Computer Science University of California Irvine CA USA

In this paper, we propose a simple and efficient mechanism to increase the throughput of an adaptive router in network-on-chip (NoC). One of the most serious disadvantages of fully adaptive wormhole routers is its performance degradation due to the routing decision time. The key idea to overcome this shortcoming is the use of different clocks in a head flit and body flits, because the body flits can be forwarded immediately and the FIFO usually operates faster than route decision logic in an adaptive router. The major contributions of this paper are: 1) a proposal of a simple and efficient mechanism to improve the performance of fully adaptive wormhole routers, 2) a quantitative evaluation of the proposed mechanism showing that the proposed one can support higher throughput than a conventional one, and 3) an evaluation of hardware overhead for the proposed router. In summary, the proposed clock boosting mechanism enhances the throughput of the original adaptive router by increasing the accepted load and decreasing the average latency in the region of effective bandwidth.

关键词： Network-on-a-chip Throughput Adaptive systems Clocks Degradation Routing Logic Proposals hardware Boosting

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Yield prediction for architecture exploration in nanometer technology nodes:: a model and case study for memory organizations

Yield prediction for architecture exploration in nanometer t...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： T. Grabner F. Catthoor M. Miranda P. Roussel A. Papanikolaou IMEC vzw Leuven Belgium

Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing violations. Conventional yield models do not allow to accurately analyze this, at least not at the system level. In this paper we propose a technique to estimate this system level yield loss for a number of alternative memory organization implementations. This can aid the designer into making educated trade-offs at the architecture level between energy consumption and parametric timing yield by using memories from different available libraries with different energy/performance characteristics considering the impact of manufacturing variations. The accuracy of this technique is very high, an average error of less than 1% is reported, which enables an early exploration of the available options.

关键词： Predictive models Timing Energy consumption Embedded system Performance loss Yield estimation Manufacturing Power system reliability Real time systems system-level design

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