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Efficient Gait Trajectory Prediction Method Based on Soft Constraint Weighted Template Matching: Work-in-Progress

Efficient Gait Trajectory Prediction Method Based on Soft Co...

引用

Proceedings of the 2023 international conference on hardware/software codesign and system synthesis

作者： Xing Liu Yifan Liu Xingjun Wang Shenzhen International Graduate School Tsinghua University Shenzhen Guangdong China

ISBN: (纸本)9798400702891

Embedded systems in exoskeletons and wearable rehabilitation devices require efficient monitoring of human gait with stringent demands for real-time and reliable performance. Gait trajectory prediction enables full-process perception of future gait patterns. The template matching approach is a promising algorithm for gait trajectory prediction. However, it has challenges in terms of template selection and dynamic stability. We developed DTW-KM Template Selection Method using the DTW distance matrix and K-means to find trajectories with generality and diversity as candidate templates. In addition, we use a matching method combining soft constraints and quadratic weighting, named ScW Template Matching Method. it can balance timeliness, stability and flexibility, and suppress gait phase and trajectory oscillations. Preliminary experimental results show that our method achieves stable prediction of 0.5--1s gait using efficient inference on embedded devices.

关键词： real time trajectory prediction template matching soft constraint

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HW-FlowQ: A Multi-Abstraction Level HW-CNN Co-design Quantization Methodology

HW-FlowQ: A Multi-Abstraction Level HW-CNN Co-design Quantiz...

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international conference on hardware/software codesign and system synthesis (CODES plus ISSS)

作者： Fasfous, Nael Vemparala, Manoj Rohit Frickenstein, Alexander Valpreda, Emanuele Salihu, Driton Nguyen Anh Vu Doan Unger, Christian Nagaraja, Naveen Shankar Martina, Maurizio Stechele, Walter Tech Univ Munich Munich Germany BMW Autonomous Driving Munich Germany Politecn Torino Turin Italy

Model compression through quantization is commonly applied to convolutional neural networks (CNNs) deployed on compute and memory-constrained embedded platforms. Different layers of the CNN can have varying degrees of numerical precision for both weights and activations, resulting in a large search space. Together with the hardware (HW) design space, the challenge of finding the globally optimal HW-CNN combination for a given application becomes daunting. To this end, we propose HW-FlowQ, a systematic approach that enables the co-design of the target hardware platform and the compressed CNN model through quantization. The search space is viewed at three levels of abstraction, allowing for an iterative approach for narrowing down the solution space before reaching a high-fidelity CNN hardware modeling tool, capable of capturing the effects of mixed-precision quantization strategies on different hardware architectures (processing unit counts, memory levels, cost models, dataflows) and two types of computation engines (bit-parallel vectorized, bit-serial). To combine both worlds, a multi-objective non-dominated sorting genetic algorithm (NSGA-II) is leveraged to establish a Pareto-optimal set of quantization strategies for the target HW-metrics at each abstraction level. HW-FlowQ detects optima in a discrete search space and maximizes the task-related accuracy of the underlying CNN while minimizing hardware-related costs. The Pareto-front approach keeps the design space open to a range of non-dominated solutions before refining the design to a more detailed level of abstraction. With equivalent prediction accuracy, we improve the energy and latency by 20% and 45% respectively for ResNet56 compared to existing mixed-precision search methods.

关键词： Convolutional neural networks multi-objective optimization hardware modeling genetic algorithms quantization

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FLASH: Fast Neural Architecture Search with hardware Optimization

FLASH: Fast Neural Architecture Search with Hardware Optimiz...

引用

international conference on hardware/software codesign and system synthesis (CODES plus ISSS)

作者： Li, Guihong Mandal, Sumit K. Ogras, Umit Y. Marculescu, Radu Univ Texas Austin Austin TX 78712 USA Univ Wisconsin Madison WI USA

Neural architecture search (NAS) is a promising technique to design efficient and high-performance deep neural networks (DNNs). As the performance requirements of ML applications grow continuously, the hardware accelerators start playing a central role in DNN design. This trend makes NAS even more complicated and time-consuming for most real applications. This paper proposes FLASH, a very fast NAS methodology that co-optimizes the DNN accuracy and performance on a real hardware platform. As the main theoretical contribution, we first propose the NN-Degree, an analytical metric to quantify the topological characteristics of DNNs with skip connections (e.g., DenseNets, ResNets, Wide-ResNets, and MobileNets). The newly proposed NN-Degree allows us to do training-free NAS within one second and build an accuracy predictor by training as few as 25 samples out of a vast search space with more than 63 billion configurations. Second, by performing inference on the target hardware, we fine-tune and validate our analytical models to estimate the latency, area, and energy consumption of various DNN architectures while executing standard ML datasets. Third, we construct a hierarchical algorithm based on simplicial homology global optimization (SHGO) to optimize the model-architecture co-design process, while considering the area, latency, and energy consumption of the target hardware. We demonstrate that, compared to the state-of-the-art NAS approaches, our proposed hierarchical SHGO-based algorithm enables more than four orders of magnitude speedup (specifically, the execution time of the proposed algorithm is about 0.1 seconds). Finally, our experimental evaluations show that FLASH is easily transferable to different hardware architectures, thus enabling us to do NAS on a Raspberry Pi-3B processor in less than 3 seconds.

关键词： Neural networks network science hardware optimization neural architecture search model-architecture co-design resource-constrained devices

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Special Session: Mitigating Side-channel Attacks through Circuit to Application Layer Approaches

Special Session: Mitigating Side-channel Attacks through Cir...

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Proceedings of the 2023 international conference on hardware/software codesign and system synthesis

作者： Nima Kavand Armin Darjani Jens Trommer Giulio Galderisi Thomas Mikolajick Nicolai Mueller Amir Moradi Chongzhou Fang Ning Miao Han Wang Sai Manoj Pudukotai Dinakarrao Houman Homayoun Benjamin Hettwer Luca Parrini Akash Kumar TU Dresden Dresden Saxony Germany Namlab gGmbH Dresden Saxony Germany Ruhr University Bochum Bochum North Rhine-Westphalia Germany UC Davis Davis California USA Temple University Philadelphia Pennsylvania USA George Mason University Fairfax Virginia USA Robert Bosch GmbH Renningen Baden-wuerttemberg Germany

ISBN: (纸本)9798400702891

Side-Channel Attacks (SCAs), which are always considered a severe threat to the security of the cryptographic circuits, today can also be employed to extract IP secrets and neural network models. Hence, developing novel security solutions at different design levels is crucial. In this paper, we explore recent countermeasures at the circuit, algorithmic, and microarchitecture levels. First, we explain how Reconfigurable Field-Effect Transistor (RFET), as a beyond CMOS technology, enables us to provide both IP and data protection against SCAs at the circuit level. Second, we investigate an automated method for generating masked circuits as an algorithmic solution, and then we review machine learning-based SCA detection mechanisms at the microarchitecture level. Finally, we discuss emerging threats of SCAs from the industrial point of view.

关键词： hardware security side-channel analysis emerging technology masking

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ESWEEK 2019 conference Report

ESWEEK 2019 Conference Report

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作者： Eles, Petru Mitra, Tulika Linköping University Sweden Department of Computer Science National University of Singapore Singapore Singapore

Embedded systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for smart, intelligent, and connected computing systems. By bringing together three leading conferences [the international conference on Compilers, Architecture, and synthesis for Embedded systems (CASES), the international conference on hardware/software codesign and system synthesis (CODES+ISSS), and the international conference on Embedded software (EMSOFT)], a special Internet of Medical Things (IoMT) day, a symposium [the international Symposium on Networks-on-Chip (NOCS)], and hottopic workshops and tutorials, ESWEEK presents the attendees with a wide range of topics unveiling state-of-the-art embedded software, embedded architectures, and embedded system designs. © 2013 IEEE.

关键词： Embedded systems

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Algorithm-hardware Co-design of Attention Mechanism on FPGA Devices

Algorithm-hardware Co-design of Attention Mechanism on FPGA ...

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international conference on hardware/software codesign and system synthesis (CODES plus ISSS)

作者： Zhang, Xinyi Wu, Yawen Zhou, Peipei Tang, Xulong Hu, Jingtong Univ Pittsburgh Swanson Sch Engn Elect & Comp Engn Pittsburgh PA 15260 USA Univ Pittsburgh Sch Comp & Informat Comp Sci Pittsburgh PA 15260 USA

Multi-head self-attention (attention mechanism) has been employed in a variety of fields such as machine translation, language modeling, and image processing due to its superiority in feature extraction and sequential data analysis. This is benefited from a large number of parameters and sophisticated model architecture behind the attention mechanism. To efficiently deploy attention mechanism on resource-constrained devices, existing works propose to reduce the model size by building a customized smaller model or compressing a big standard model. A customized smaller model is usually optimized for the specific task and needs effort in model parameters exploration. Model compression reduces model size without hurting the model architecture robustness, which can be efficiently applied to different tasks. The compressed weights in the model are usually regularly shaped (e.g. rectangle) but the dimension sizes vary (e.g. differs in rectangle height and width). Such compressed attention mechanism can be efficiently deployed on CPU/GPU platforms as their memory and computing resources can be flexibly assigned with demand. However, for Field Programmable Gate Arrays (FPGAs), the data buffer allocation and computing kernel are fixed at run time to achieve maximum energy efficiency. After compression, weights are much smaller and different in size, which leads to inefficient utilization of FPGA on-chip buffer. Moreover, the different weight heights and widths may lead to inefficient FPGA computing kernel execution. Due to the large number of weights in the attention mechanism, building a unique buffer and computing kernel for each compressed weight on FPGA is not feasible. In this work, we jointly consider the compression impact on buffer allocation and the required computing kernel during the attention mechanism compressing. A novel structural pruning method with memory footprint awareness is proposed and the associated accelerator on FPGA is designed. The experimental resu

关键词： Co-design algorithm hardware attention transformer FPGA tops

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Work-in-Progress: Improving Security and Maintainability in Modular Embedded systems with hardware Support

Work-in-Progress: Improving Security and Maintainability in ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Maja Malenko Leandro Batista Ribeiro Marcel Baunach Graz University of Technology Austria

ISBN: (纸本)9781665417242

The current trend of transforming static embedded systems into open platforms (in which several software providers are able to directly load their software) drives the need to design and implement modular embedded software. Additionally, a myriad of embedded devices are expected to operate and provide services for years, or even decades, while remaining correct and secure at all times. Therefore, one of the emerging challenges for highly adaptive embedded computing platforms is to offer dynamic software composition at runtime and internal device housekeeping, which in conjunction improve device maintainability. We propose a hardware/software co-designed technique to improve both security and maintainability in modular embedded systems.

关键词： Embedded computing Runtime Market research hardware Security Embedded software

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Work-in-Progress: A Study of Transistor Degradation in Cyber-Physical system Control Devices

Work-in-Progress: A Study of Transistor Degradation in Cyber...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Spencer Millican SueAnne Griffith Samuel Ginn College of Engineering Auburn University Auburn Alabama USA

ISBN: (纸本)9781665417242

This work presents a plan for investigating transistor aging and degradation in cyber physical systems under attack. The authors discuss the importance of such concerns, particularly with regard to negative bias temperature instability, and an approach to demonstrate the adverse effects of a cyber-attack resulting in premature aging of transistors within a system's digital controllers.

关键词： Degradation Negative bias temperature instability Thermal variables control Aging Cyber-physical systems Transistors

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MARS: mm Wave-based Assistive Rehabilitation system for Smart Healthcare

MARS: mm Wave-based Assistive Rehabilitation System for Smar...

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international conference on hardware/software codesign and system synthesis (CODES plus ISSS)

作者： An, Sizhe Ogras, Umit Y. Univ Wisconsin Dept Elect & Comp Engn Madison WI 53706 USA

Rehabilitation is a crucial process for patients suffering from motor disorders. The current practice is performing rehabilitation exercises under clinical expert supervision. New approaches are needed to allow patients to perform prescribed exercises at their homes and alleviate commuting requirements, expert shortages, and healthcare costs. Human joint estimation is a substantial component of these programs since it offers valuable visualization and feedback based on body movements. Camera-based systems have been popular for capturing joint motion. However, they have high-cost, raise serious privacy concerns, and require strict lighting and placement settings. We propose a millimeter-wave (mmWave)-based assistive rehabilitation system (MARS) for motor disorders to address these challenges. MARS provides a low-cost solution with a competitive object localization and detection accuracy. It first maps the 5D time-series point cloud from mmWave to a lower dimension. Then, it uses a convolution neural network (CNN) to estimate the accurate location of human joints. MARS can reconstruct 19 human joints and their skeleton from the point cloud generated by mmWave radar. We evaluate MARS using ten specific rehabilitation movements performed by four human subjects involving all body parts and obtain an average mean absolute error of 5.87 cm for all joint positions. To the best of our knowledge, this is the first rehabilitation movements dataset using mmWave point cloud. MARS is evaluated on the Nvidia Jetson Xavier-NX board. Model inference takes only 64 mu s and consumes 442 mu J energy. These results demonstrate the practicality of MARS on low-power edge devices.

关键词： Human pose estimation point cloud millimeter wave smart healthcare

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Towards High Performance and Accurate BNN Inference on FPGA with Structured Fine-grained Pruning

Towards High Performance and Accurate BNN Inference on FPGA ...

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IEEE international conference on Computer-Aided Design

作者： Keqi Fu Zhi Qi Jiaxuan Cai Xulong Shi Electrical Engineering Dept. National ASIC System Engineering Research Center Southeast University China

As the extreme case of quantization networks, Binary Neural Networks (BNNs) have received tremendous attention due to many hardware-friendly properties in terms of storage and computation. To reach the limit of compact models, we attempt to combine binarization with pruning techniques, further exploring the redundancy of BNNs. However, coarse-grained pruning methods may cause server accuracy drops, while traditional fine-grained ones induce irregular sparsity hard to be utilized by hardware. In this paper, we propose two advanced fine-grained BNN pruning modules, i.e., structured channel-wise kernel pruning and dynamic spatial pruning, from a joint perspective of algorithm and hardware. The pruned BNN models are trained from scratch and present not only a higher precision but also a high degree of parallelism. Then, we develop an accelerator architecture that can effectively exploit the sparsity caused by our algorithm. Finally, we implement the pruned BNN models on an embedded FPGA (Ultra96v2). The results show that our software and hardware codesign achieves 5.4x inference-speedup than the baseline BNN, with higher resource and energy efficiency compared with prior FPGA implemented BNN works.

关键词： Heuristic algorithms Neural networks software algorithms Redundancy Accelerator architectures hardware Energy efficiency

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