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Future wireless convergence platforms

Future wireless convergence platforms

引用

international conference on hardware/software codesign and system synthesis

作者： Glossner, J Moudgill, M Iancu, D Nacer, G Jintukar, S Stanley, S Samori, M Raja, T Schulte, M Vassiliadis, S Sandbridge Technol Inc White Plains NY 10601 USA

ISBN: (纸本)1595931619

As wireless platforms converge to multimedia systems, architectures must converge to support voice, data, and video applications. From a processor architecture perspective, support for signal processing (both audio and video), control code, and Java execution will be required in a convergent device. Traditionally, wireless communications systems have been implemented in hardware. Convergent devices must be able to roam seamlessly across multiple communications systems. To avoid excessive hardware costs, a software Defined Radio (SDR) approach offers a programmable and dynamically reconfigurable method of reusing hardware to implement physical layer processing. In this paper, we discuss trends in wireless platforms which are inherently convergence platforms. We also present the Sandbridge state-of-the-art example platform that supports both communications and multimedia applications processing. The architecture efficiently executes Java, Digital Signal Processing (DSP), and control code. Architectural features that reduce power dissipation and enable real-time processing are described. All of the communications and multimedia processing is executed completely in software without specialized hardware support. The processor is programmed in C with supercomputer-class compiler support for automatic vectorization, multithreading, and DSP semantic analysis.

关键词： software defined radio wireless digital signal processors

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FlexPath NP - A network processor concept with application-driven flexible processing paths

FlexPath NP - A network processor concept with application-d...

引用

international conference on hardware/software codesign and system synthesis

作者： Ohlendorf, R Herkersdorf, A Wild, T Tech Univ Munich D-80290 Munich Germany

ISBN: (纸本)1595931619

In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP) application sub-functions onto both SW programmable processor (CPU) resources and (re-)configurable HW building blocks, such that different packet flows are forwarded via different, optimized processing paths through the NP. Packets with well understood, relatively simple processing requirements may even bypass the central CPU complex (AutoRoute). In consequence, CPU processing resources are more effectively used and the overall NP performance and throughput are improved compared to conventional NP architectures. We present analytical performance estimations to quantify the performance advantage of FlexPath (expressed as available CPU instructions for each packet traversing the CPUs) and introduce a platform-based system on Programmable Chip (SoPC) based architecture which implements the FlexPath NP concept.

关键词： network processors application-specific architectures hardware accelerators dynamically reconfigurable processors IP networking

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What will system level design be when it grows up? 05

What will system level design be when it grows up?

引用

international conference on hardware/software codesign and system synthesis

作者： Martin, G Gajski, D Goodwin, D Lysaght, P Marwedel, P Muller, M Weiser, J Tensilica UC Irvine Xilinx Research University of Dortmund Germany ARM UK IBM

ISBN: (纸本)1595931619

We have seen a growing new interest in Electronic system Level (ESL) architectures, design methods, tools and implementation fabrics in the last few years. But the picture of what types and approaches to building embedded systems will become the most widely-accepted norms in the future remains fuzzy at best. Everyone want to know where systems and system design is going "when it grows up", if it ever "grows up". Some of the key questions that need to be answered include which applications will be key system drivers, what SW & HW architectures will suit best, how programmable and configurable will they be, will systems designers need to deal with physical implementation issues or will that be hidden behind fabric abstractions and programming models, and what will those abstractions and models be? Moreover, will these abstractions stabilize and be still useful as the underlying technology keeps developing at high *** panel consists of proponents of a number of alternative visions for where we will end up, and how we will get there.

关键词： system-level compensation parametric yield process variability

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A unified approach to constrained mapping and routing on network-on-chip architectures 05

A unified approach to constrained mapping and routing on net...

引用

international conference on hardware/software codesign and system synthesis

作者： Hansson, A Goossens, K Radulescu, A Lund Univ Dept Informat Technol S-22100 Lund Sweden

ISBN: (纸本)1595931619

One of the key steps in Network-on-Chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called Unified MApping, Routing and Slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder system-on-Chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach.

关键词： system-on-chip network-on-chip quality-of-service mapping routing

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Automatic network generation for system-on-chip communication design 05

Automatic network generation for system-on-chip communicatio...

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3rd IEEE/acm/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

作者： Shin, Dongwan Gerstlauer, Andreas Dömer, Rainer Gajski, Daniel D. Center for Embedded Computer Systems University of California Irvine CA 92697 United States

ISBN: (纸本)1595931619

With growing system complexities, system-level communication design is becoming increasingly important and advanced, network-oriented communication architectures become necessary. In this paper, we extend previous work on automatic communication refinement to support non-traditional, network-oriented architectures beyond a single bus. From an abstract description of the desired communication channels, the refinement tools automatically generate executable models and implementations of the system communication at various levels of abstraction. Experimental results show that significant productivity gains can be, achieved, demonstrating the effectiveness of the approach for rapid, early communication design space exploration. Copyright 2005 acm.

关键词： Communication systems

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Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines

Enabling unrestricted automated synthesis of portable hardwa...

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3rd IEEE/acm/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

作者： Vuletić, Miljan Pozzi, Laura Dubach, Christophe Lenne, Paolo School of Computer and Communication Sciences CH-1015 Lausanne Switzerland

ISBN: (纸本)1595931619

The performance of virtual machines (e.g., Java Virtual Machines - JVMs) can be significantly improved when critical code sections (e.g., Java bytecode methods) are migrated from software to reconfigurable hardware. In contrast to the compile-once-run-anywhere concept of virtual machines, reconfigurable applications lack portability and transparent SW/HW interfacing: applicability of accelerated hardware solutions is often limited to a single platform. In this work, we apply a virtualisation layer that provides portable and seamless integration of hardware and software components to a JVM platform, making it capable of accelerating any Java bytecode method by using platform-independent hard-ware accelerators. The virtualisation layer not only improves portability of accelerated Java bytecode applications, but also supports runtime optimisations and enables unrestricted automated synthesis of arbitrary Java bytecode to hardware. To show the advantages and measure the limited overheads of our approach, we run several accelerated applications (handwritten and synthesised) on a real embedded platform. We also show our synthesis flow and discuss its advanced features fostered by the virtualisation layer. Copyright 2005 acm.

关键词： Portable equipment

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Rappit: Framework for synthesis of host-assisted scripting engines for adaptive embedded systems

Rappit: Framework for synthesis of host-assisted scripting e...

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3rd IEEE/acm/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

作者： Hahn, Jiwon Xie, Qiang Chou, Pai H. Center for Embedded Computer Systems University of California Irvine United States

ISBN: (纸本)1595931619

Scripting is a powerful, high-level, cross-platform, dynamic, easy way of composing software modules as black boxes. Unfortunately, the high runtime overhead has prevented scripting from being widely adopted in embedded applications. This work proposes to overcome these obstacles by synthesizing light-weight, host-assisted scripting engines for embedded systems. The result is dramatically shortened development cycle due to the much higher-level abstraction, interactive access and dynamic reconfigurability, robust in-field software upgradability, and compact code size. This framework has been successfully applied to ultra low-power sensor nodes with under 10KB of program memory to high-performance platforms with fast Ethernet. Copyright 2005 acm.

关键词： Embedded systems

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Shift buffering technique for automatic code synthesis from synchronous dataflow graphs 05

Shift buffering technique for automatic code synthesis from ...

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international conference on hardware/software codesign and system synthesis

作者： Oh, H Dutt, N Ha, S Univ Calif Irvine CECS Irvine CA 92697 USA

ISBN: (纸本)1595931619

This paper proposes a new efficient buffer management technique called shift buffering for automatic code synthesis from synchronous dataflow graphs (SDF). Two previous buffer management methods, linear buffering and modulo (or circular) buffering, assume that samples are queued in the arc buffers in the arrival order and are accessed by moving the buffer indices. But both methods have significant overhead for general multi-rate systems: the linear buffering method requires large size buffers and the modulo buffering method needs run-time overhead of buffer index computation. The proposed shift buffering method shifts samples rather than moving buffer indices. We develop optimal shift buffering algorithms to minimize the number of shifted samples. Our experimental results show that the proposed algorithm saves up to 90% of performance overhead while requiring the same amount of buffer memory as modulo buffering. Considering the sample copy overhead, shift buffering is applicable when memory size is more crucial than performance overhead, and the shifting overhead is less than the modulo addressing overhead. Another advantage of the shift buffering technique is that it supports the library code written with the linear buffering assumption, which is practically more important.

关键词： buffer management automatic code synthesis synchronous dataflow shift buffering modulo buffering

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system design extreme makeover 05

System design extreme makeover

引用

3rd acm/IEEE international conference on Formal Methods and Models for Co-Design

作者： Gajski, DD Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92697 USA

ISBN: (纸本)0780392272

With complexities of systems-on-chip (SOCs) rising almost daily, the design community has been searching for a new methodology that can handle given complexities with increased productivity and decreased time-to-market. In order to find a solution for the system-level design flow, we must look at the system gap between SW and HW designs and then try to bridge this gap by developing a design flow that is based on common principles applicable to software and hardware. In order to achieve this design flow we can define design process by using the concepts found in standard algebras which, in turn, allows us to define design models more formally with clean unambiguous semantics. Such clean semantics allows automatic model generation, simplifies synthesis algorithms and verification techniques.

关键词： system-level design flow formal verification technique hardware-software codesign automatic model generation

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Service dependency graph, an efficient model for hardware/software interfaces modeling and generation for SoC design

Service dependency graph, an efficient model for hardware/so...

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3rd IEEE/acm/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

作者： Sarmento, Adriano Kriaa, Lobna Grasset, Arnaud Youssef, Mohamed-Wassim Bouchhima, Aimen Rousseau, Frederic Cesario, Wander Jerraya, Ahmed Amine TIMA Laboratory SLS Group 46 avenue Felix Viallet Grenoble Cedex 38031 France

ISBN: (纸本)1595931619

Complex systems-on-chip are designed by interconnecting pre-designed hardware (HW) and software (SW) components. During the design cycle, a global model of the SoC may be composed of HW and SW models at different abstraction levels. Designing HW/SW interfaces to interconnect SoC components is a source of design bottlenecks. This paper describes a service-based model enabling systematic design and co-simulation of HW/SW interfaces for SoC design. This model, called Service dependency graph (SDG) allows modeling of complex and application-specific interfaces. We present also a model generator that can automatically build HW/SW interfaces based on service and resource requirements described by the SDG. This approach has been applied successfully on me design of an MPEG-4 encoder. Additionally the SDG seems to be an excellent intermediate representation for the design automation of HW/SW interfaces. Copyright 2005 acm.

关键词： Microprocessor chips

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