检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

995 篇 会议
40 篇 期刊文献

馆藏范围

1,035 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

542 篇 工学
- 512 篇 计算机科学与技术...
- 403 篇 软件工程
- 109 篇 电气工程
- 103 篇 电子科学与技术（可...
- 48 篇 信息与通信工程
- 40 篇 控制科学与工程
- 26 篇 机械工程
- 12 篇 建筑学
- 11 篇 动力工程及工程热...
- 7 篇 材料科学与工程（可...
- 6 篇 光学工程
- 6 篇 安全科学与工程
- 5 篇 土木工程
- 4 篇 生物工程
- 3 篇 生物医学工程（可授...
- 2 篇 力学（可授工学、理...
- 2 篇 仪器科学与技术
- 2 篇 化学工程与技术
113 篇 理学
- 68 篇 数学
- 46 篇 系统科学
- 11 篇 物理学
- 8 篇 统计学（可授理学、...
- 4 篇 生物学
67 篇 管理学
- 56 篇 管理科学与工程(可...
- 20 篇 工商管理
- 12 篇 图书情报与档案管...
10 篇 法学
- 6 篇 社会学
- 4 篇 法学
7 篇 艺术学
- 7 篇 设计学（可授艺术学...
5 篇 经济学
- 5 篇 应用经济学
1 篇 医学

主题

207 篇 hardware
113 篇 computer archite...
94 篇 embedded system
67 篇 application soft...
60 篇 embedded systems
60 篇 permission
55 篇 system-on-a-chip
51 篇 computational mo...
48 篇 field programmab...
47 篇 algorithm design...
47 篇 software
41 篇 energy consumpti...
40 篇 costs
37 篇 system-on-chip
34 篇 real time system...
34 篇 space exploratio...
34 篇 embedded softwar...
32 篇 timing
32 篇 high level synth...
31 篇 system-level des...

机构

8 篇 center for embed...
8 篇 department of el...
7 篇 univ calif river...
7 篇 department of co...
6 篇 school of comput...
6 篇 arizona state un...
6 篇 center for embed...
6 篇 institute for in...
5 篇 princeton univ d...
5 篇 school of inform...
5 篇 philips research...
5 篇 university of er...
5 篇 nec laboratories...
4 篇 natl taiwan univ...
4 篇 department of co...
4 篇 politecn torino ...
4 篇 carnegie mellon ...
4 篇 tu braunschweig
4 篇 university of ca...
4 篇 university of do...

作者

9 篇 sri parameswaran
9 篇 ogras umit y.
9 篇 nikil dutt
8 篇 leupers rainer
7 篇 rolf ernst
7 篇 teich juergen
7 篇 robert p. dick
7 篇 parameswaran sri
6 篇 jiang wei
6 篇 dick robert p.
6 篇 dutt nikil
6 篇 mitra tulika
6 篇 rainer leupers
6 篇 andreas gerstlau...
6 篇 jha niraj k.
5 篇 pasricha sudeep
5 篇 gerd ascheid
5 篇 greg stitt
5 篇 jinyu zhan
5 篇 ernst rolf

语言

1,034 篇 英文
1 篇 其他

检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

共 1035 条记录，以下是711-720 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Highly flexible multi-mode system synthesis 05

Highly flexible multi-mode system synthesis

引用

3rd IEEE/acm/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

作者： Kumar, Vinu Vijay Lach, John Texas Instruments M/S 714 12203 Southwest Fr. Stafford TX 77477 United States Department of Electrical and Computer Engineering University of Virginia 351 McCormick Rd. Charlottesville VA 22904 United States

ISBN: (纸本)1595931619

Multi-mode systems have emerged as an area- and power-efficient approach to implementing multiple time-wise mutually exclusive algorithms and applications in a single hardware space. These systems have limited flexibility and temporal separation between modes is achieved by changing only the dataflow between components. This paper presents a synthesis methodology for integrating flexible components and controllers into primarily fixed logic multi-mode systems thereby increasing their overall flexibility and efficiency. The components are built using a technique called small-scale reconfigurability that provides the necessary flexibility without the penalties associated with generalpurpose reconfigurable logic. The reconfiguration latency is small enabling both inter-mode and intra-mode reconfiguration of components. Datapath and controller area and power consumption are reduced beyond what is provided in current multi-mode systems using this methodology, without sacrificing performance. The results show an average 7% reduction in datapath component area, 26% reduction in register area, 36% reduction in interconnect MUX cost, and a 68% reduction in the number of controller signals for a set of benchmark 32-bit signal processing applications. There is also an average 38% increase in component utilization. Copyright 2005 acm.

关键词： Algorithms

来源：评论

学校读者我要写书评

暂无评论

High-level synthesis for large bit-width multipliers on FPGAs: A case study

High-level synthesis for large bit-width multipliers on FPGA...

引用

3rd IEEE/acm/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

作者： Quan, Gang Davis, James P. Devarkal, Siddhaveerasharan Buell, Duncan A. Department of Computer Science and Engineering University of South Carolina Columbia SC 29208 United States

ISBN: (纸本)1595931619

In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are required for cryptography and error correction circuits for more secure and reliable transmissions over highly insecure and/or noisy channels in networking and multimedia applications. The design space for these circuits is very large when integer multiplication on large operands is carried out hierarchically. In this paper, we explore automated synthesis of high bit-width unsigned integer multiplier circuits by defining and validating an estimator function used in search and analysis of the design space of such circuits. We focus on analysis of a hybrid hierarchical multiplier scheme that combines the throughput advantages of parallel multipliers and the resource cost-effectiveness of serial ones. We present an analytical model that rapidly predicts timing and resource usage for selected model candidates. We evaluate the estimator model in the design of a practical application, a 256-bit elliptic curve adder implemented on a Xilinx FPGA fabric. We show that our estimator allows implementation of fast, efficient circuits, where resultant designs provide order-of-magnitude performance improvements when compared with that of software implementations on a high performance computing platform. Copyright 2005 acm.

关键词： Field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

hardware and software architectures for the Cell processor 05

Hardware and software architectures for the Cell processor

引用

3rd IEEE/acm/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

作者： Hofstee, Peter Day, Michael IBM Systems and Technology Group Austin TX United States

ISBN: (纸本)1595931619

The Cell processor is a first instance of a new family of processors intended for the broadband era. The processors will find early use in game systems (PlayStation3™), a variety of other consumer electronics applications, a wide variety of embedded applications, and various forms of computational accelerators. Cell is a non-homogeneous multi-core processor, with one POWER processor core (two threads) dedicated to the operating system and other control functions, and eight synergistic processors optimized for compute-intensive applications. Cell addresses two of the main limiters to microprocessor performance: increased memory latency, and performance limitations induced by system power limits. Memory latency is addressed by introducing another software-managed level of private "local" memory, in between the private registers and shared system memory. Data is transferred between this local memory and shared memory with asynchronous cache coherent DMA commands, and synergistic processor load and store commands access the local store only. This organization of memory makes it possible for the Cell processor to have over 100 memory transactions in flight at the same time, more than enough to cover memory latency. Power limitations are addressed by two main mechanisms;a non-homogeneous multi-core organization, and an ultra high-frequency design that allows the chip to be operated at 3.2GHz at low voltage. The Cell processor supports many of today's programming models by introducing the concept of heterogeneous tasks or threads. Both Power processor and SPE based threads can be managed by the operating system and effectively utilized by applications starting with the relatively straightforward function offload model to the more complex single source heterogeneous parallel programming model. Cell achieves between one and two orders of magnitude of performance advantage over conventional single-core processors on compute-intensive (32-bit) applications, by permitting progr

关键词： Computer architecture

来源：评论

学校读者我要写书评

暂无评论

Enhancing security through hardware-assisted run-time validation of program data properties 05

Enhancing security through hardware-assisted run-time valida...

引用

3rd IEEE/acm/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

作者： Arora, Divya Raghunathan, Anand Ravi, Srivaths Jha, Niraj K. Dept. of Electrical Engineering Princeton University Princeton NJ 08544 United States NEC Laboratories America Princeton NJ 08540 United States

ISBN: (纸本)1595931619

The growing number of information security breaches in electronic and computing systems calls for new design paradigms that consider security as a primary design objective. This is particularly relevant in the embedded domain, where the security solution should be customized to the needs of the target system, while considering other design objectives such as cost, performance, and power. Due to the increasing complexity and shrinking design cycles of embedded software, most embedded systems present a host of software vulnerabilities that can be exploited by security attacks. Many attacks are initiated by causing a violation in the properties of data (e.g., integrity, privacy, access control rules, etc.) associated with a "trusted" program that is executing on the system, leading to a range of undesirable effects. In this work, we develop a general framework that provides security assurance against a wide class of security attacks. Our work is based on the observation that a program's permissible behavior with respect to data accesses can be characterized by certain properties. We present a hardware/software approach wherein such properties can be encoded as data attributes and enforced as security policies during program execution. These policies may be application-specific (e.g., access control for certain data structures), compiler-generated (e.g., enforcing that variables are accessed only within their scope), or universally applicable to all programs (e.g., disallowing writes to unallocated memory). We show how an embedded system architecture can support, such policies by (i) enhancing the memory hierarchy to represent the attributes of each datum as security tags that are linked to it through its lifetime, and (ii) adding a configurable hardware checker that interprets the semantics of the tags and enforces the desired security policies. We evaluated the effectiveness of the proposed architecture in enforcing various security policies for several embedded bench

关键词： Data reduction

来源：评论

学校读者我要写书评

暂无评论

FIDES: An advanced chip multiprocessor platform for secure next generation mobile terminals

FIDES: An advanced chip multiprocessor platform for secure n...

引用

3rd IEEE/acm/IFIP international conference on hardware/software codesign and systems synthesis CODES+ISSS 2005

作者： Inoue, Hiroaki Ikeno, Akihisa Kondo, Masaki Sakai, Junji Edahiro, Masato System Devices Research Laboratories NEC Corporation 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan NEC Informatec Systems Ltd. 3-2-1 Sakado Kawasaki Kanagawa 213-0012 Japan

ISBN: (纸本)1595931619

We propose a secure platform on a chip multiprocessor, known as FIDES, in order to enable next generation mobile terminals to execute downloaded native applications for Linux. Its most important feature is the higher security based on multi-grained separation mechanisms: coarse-grained processor-level separation of the basic-function domain from other domains for such downloaded applications, medium-grained OS-level separation, and fine-grained process-level separation within SELinux. Four new technologies, which include three enhancements to SELinux, support the FIDES platform: 1) bus filter logic for processor-level separation can be implemented as a small logic, 2) XIP kernels for memory-efficient OS-level separation can reduce memory requirements by 182%, 3) policy separation for enhanced process-level separation can apply policies 2.1 times faster at system bootup, and 4) dynamic access control can provide secure Inter-Domain Communications (IDCs) with an overhead of only 4% for IDC system calls. We implemented SELinuxes on an ARM-based multiprocessor. Therefore, the best-suited platform to secure next generation mobile terminals is the FIDES platform, which can provide higher security as well as higher performance and lower power consumption on chip multiprocessors leading the current technology trend of microprocessors. Copyright 2005 acm.

关键词： Microprocessor chips

来源：评论

学校读者我要写书评

暂无评论

A UAV-based computer engineering capstone senior design project

A UAV-based computer engineering capstone senior design proj...

引用

IEEE international conference on Microelectronic systems Education

作者： Klenke, RH Virginia Commonwealth Univ Dept Elect Engn Richmond VA 23284 USA

ISBN: (纸本)0769523749

This paper describes the development of an Unmanned Aerial Vehicle (UAV) for a capstone senior design project in computer engineering. The student portion of the project involved the development of a flight control system for the UAV The flight control system was based on the Atmel FPSLIC device. The FPSLIC contains an 8-bit A T R microcontroller and a 40K gate-equivalent Field Programmable Gate Array which allowed the students to implement components of the flight control system in both hardware and software. The overall system architecture and implementation of the flight control system are described.

关键词： aircraft control computer science education control system synthesis engineering education field programmable gate arrays hardware-software codesign microcontrollers student experiments FPGA capstone senior design project computer engineering field progr Field programmable gate arrays Flight control systems COMPUTER ENGINEERING Aircraft control Microcontrollers Student experiments hardware/software co-design control system synthesis computer science education Engineering education

来源：评论

学校读者我要写书评

暂无评论

Performance evaluation of a noise canceller filter to be used in codesign techniques

Performance evaluation of a noise canceller filter to be use...

引用

EUROCON 2005 - The international conference on Computer as a Tool

作者： De Icaya, E. Martínez Rodellar, V. Peinado, V. García, V. Díaz, A. González, C. Universidad Politécnica de Madrid Km7 Carretera de Valencia 28031. Madrid Spain UPM Campus de Montegancedo S/n Boadilla del Monte 28660 Madrid Spain

ISBN: (纸本)142440049X

codesign techniques allow exploring different design alternatives at the system level specification by means of realizations in hardware and software for each composing blocks, and thus to evaluate the system performance before choosing the final implementation. In this paper the performance estimation in terms of area, time and power dissipation of a noise canceller filter both in software and hardware implementations is presented. The approximation has consisted of the specification of the problem in ANSI C and its transformation through synthesis tools into assembler code for the DSP 56000 microprocessor and into RTL VHDL synthesizable code by means of SPARK [3]. Also more precise hardware estimation for FPGA's and standard cells Is presented. © 2005 IEEE.

关键词： Adaptive filtering

来源：评论

学校读者我要写书评

暂无评论

hardware/software co-design using hierarchical platform-based design method 05

Hardware/software co-design using hierarchical platform-base...

引用

10th Asia and South Pacific Design Automation conference

作者： Xiong, Zhihui Li, Sikan Chen, Jihua Univ Def Technol Sch Comp Sci Changsha 410073 Peoples R China

ISBN: (纸本)0780387368

A Hierarchical Platform-Based Design (Hi-PBD) method is put forward for SoC system design. This method divides SoC system design flow into three levels (i.e. system model level, virtual components level and real components level) to achieve separation of function from structure and separation of computation from communication. Hi-PBD defines two mapping processes (i.e. design planning and virtual-real synthesis) to go through all the three design levels. Hi-PBD supports reuse of both the three level design templates and the two mapping results, which increased reusing efficiency greatly. Besides, Hi-PBD boosts up design flexibility by means of supporting revision at all the three levels, and ensures the final design target satisfies performance requirements through a novel performance constraints transmission strategy. Experiments indicate Hi-PBD method improves SoC high level design efficiency by 30%-40%, and this method achieves platform template reuse ratio by 75%-90%.

关键词： hardware-software codesign system-on-chip integrated circuit design circuit CAD logic CAD hardware-software co-design hierarchical platform-based design method Hi-PBD method SoC system design flow system model level virtual components level real components level mapping process design planning virtual-real synthesis performance constraints transmission strategy SoC high level design efficiency platform template reuse ratio

来源：评论

学校读者我要写书评

暂无评论

Developing design tools for biological and biomedical applications of micro- and nano-technology

Developing design tools for biological and biomedical applic...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Jacob White Electrical Engineering and Computer Science Research Laboratory of Electronics Massachusetts Institute of Technology Cambridge MA USA

This short paper, an update of [75], is intended to provide a brief summary and extensive references on biological applications for micro- and nano-machining, as well as the computer-aided design challenges generated ... 详细信息

关键词： Nanobioscience Design automation Nanoscale devices Micromechanical devices Nanoelectromechanical systems Application software Electrostatics Biology Gene expression Prototypes

来源：评论

学校读者我要写书评

暂无评论

A core flight software system

A core flight software system

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Jonathan Wilmot Flight Software Branch Goddard Space Flight Center NASA Greenbelt MD USA

No two flight missions are alike, hence, development and on-orbit software costs are high. software portability and adaptability across hardware platforms and operating systems has been minimal at best. Standard interfaces across applications and/or common applications are almost non-existent. To reduce flight software costs, these issues must be addressed. This presentation describes how the Flight software Branch at Goddard Space Flight Center has architected a solution to these problems.

关键词： software systems Application software Operating systems Computer architecture Costs hardware Space vehicles Embedded software software architecture Plugs

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共104页 << < 68 69 70 71 72 73 74 75 76 77 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：