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Automatic network generation for system-on-chip communication design

Automatic network generation for system-on-chip communicatio...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Andreas Gerstlauer Daniel D. Gajski Rainer Domer Dongwan Shin Center for Embedded Computer Systems University of California Irvine CA USA

With growing system complexities, system-level communication design is becoming increasingly important and advanced, network-oriented communication architectures become necessary. In this paper, we extend previous work on automatic communication refinement to support non-traditional, network-oriented architectures beyond a single bus. From an abstract description of the desired communication channels, the refinement tools automatically generate executable models and implementations of the system communication at various levels of abstraction. Experimental results show that significant productivity gains can be achieved, demonstrating the effectiveness of the approach for rapid, early communication design space exploration.

关键词： system-on-a-chip Network topology system-level design Permission Message passing Computer networks Embedded computing Computational modeling Computer simulation Time to market

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Future processors: flexible and modular

Future processors: flexible and modular

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Jeff Welser Charlie Johnson IBM Rochester MN USA IBM San Jose CA USA

The ability to continue increasing processor frequency and single thread performance is being severely limited by exponential increases in leakage and active power. To continue to improve system performance, future designs will rely on increasing numbers of smaller, more power efficient cores and special purpose accelerators integrated on a chip. In this paper, we describe how these trends are leading to more modular, SoC-like designs for future processor chips, which can still achieve very high throughput performance while using simplified components and a cost efficient design methodology.

关键词： Frequency Yarn Microprocessors Circuits Pipeline processing Logic devices Latches Transistors Logic design system performance

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Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines

Enabling unrestricted automated synthesis of portable hardwa...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Laura Pozzi Paolo Ienne Christophe Dubach Miljan VuletiC School of Computer and Communication Sciences Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

The performance of virtual machines (e.g., Java Virtual Machines---JVMs) can be significantly improved when critical code sections (e.g., Java bytecode methods) are migrated from software to reconfigurable hardware. In contrast to the compile-once-run-anywhere concept of virtual machines, reconfigurable applications lack portability and transparent SW/HW interfacing: applicability of accelerated hardware solutions is often limited to a single platform. In this work, we apply a virtualisation layer that provides portable and seamless integration of hardware and software components to a Java Virtual Machine platform, making it capable of accelerating any Java bytecode method by using platform-independent hardware accelerators. The virtualisation layer not only improves portability of accelerated Java bytecode applications, but also supports runtime optimisations and enables unrestricted automated synthesis of arbitrary Java bytecode to hardware. To show the advantages and measure the limited overheads of our approach, we run several accelerated applications (handwritten and synthesised) on a real embedded platform. We also show our synthesis flow and discuss its advanced features fostered by the virtualisation layer.

关键词： hardware Virtual machining Application software Java Acceleration Field programmable gate arrays software performance Permission Microprocessors Programmable logic arrays

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Comparing the size of .NET applications with native code

Comparing the size of .NET applications with native code

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Erven Rohou Roberto Costa STMicroelectronics Manno Switzerland

Byte-code based languages are slowly becoming adopted in embedded domains because of improved security and portability. Another potential reason for their adoption is the reputation for smaller code size than native. This is critical in contexts in which a small memory footprint is crucial to reduce production costs. This paper compares the code size of applications compiled for .NET framework with the same natively compiled for various processors. The paper shows that the assumption of an impressive code size reduction is not reachable and it suggests that the adoption of such languages in embedded contexts be justified by additional arguments. The paper also studies the reasons for this and it compares with the compression ratios achievable for various applications through alternative techniques.

关键词： Java Computer languages Libraries ISO standards Security Runtime environment Application software Computer aided manufacturing Permission Yarn

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Dynamic phase analysis for cycle-close trace generation

Dynamic phase analysis for cycle-close trace generation

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Rajesh Gupta Brad Calder Jeremy Lau Cristiano Pereira Department of Computer Science and Engineering University of California San Diego USA

For embedded system development, several companies provide cross-platform development tools to aid in debugging, prototyping and optimization of programs. These are full system emulation systems that can emulate the final binary to be run on the real board, its operating system and devices. Many of these emulation systems do not provide cycle level information due to the time consuming nature of cycle accurate *** this paper we propose a method to provide Cycle-Close Traces of cycle-level statistics for the complete execution of the program in orders of magnitude less time than performing full cycle accurate simulation, with an average error of 3.2%. Our approach uses dynamic phase analysis to generate targeted cycle-close simulation samples. Detailed simulation results for these samples are used to produce fast cycle-close traces during a program's execution, so the user can also watch, pause and debug the currently executing code and its corresponding architecture performance characteristics at any point during execution.

关键词： Analytical models Emulation software debugging software performance Embedded system Operating systems hardware Permission Computer science Design engineering

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hardware/software partitioning of software binaries: a case study of H.264 decode

Hardware/software partitioning of software binaries: a case ...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Gordon McGregor Brian Einloth Frank Vahid Greg Stitt Department of Computer Science and Engineering University of California Riverside USA Center for Embedded Computer Systems University of California Irvine USA Freescale Semiconductor Inc. USA

We describe results of a case study whose intent was to determine whether new techniques for hardware/software partitioning of an application's binary are competitive with partitioning at the C source code level. While such competitiveness has been shown previously for standard benchmark suites involving smaller or unoptimized applications, the case study instead focuses on a complete 16,000-line highly-optimized commercial-grade application, namely an H.264 video decoder. The several month study revealed that binary partitioning was indeed competitive, achieving nearly identical 2.5x speedups as source level partitioning, compared to a standard microprocessor. Furthermore, the study revealed that several simple C-level coding modifications, including pass by value-return, function specialization, algorithmic specialization, hardware-targeted reimplementation, global array elimination, hoisting and sinking of error code, and conversion to explicit control flow, could lead to improved application speedups approaching 7x for both source level and binary level partitioning.

关键词： hardware Decoding Microprocessors Embedded software Field programmable gate arrays Application software software performance Kernel Partitioning algorithms Embedded system

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A power estimation methodology for systemC transaction level models

A power estimation methodology for systemC transaction level...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Vijay Narayanan Ing-chao Lin Nagu Dhanwada IBM Electronic Design Automation Systems and Technology Group Hopewell Junction NY USA Department of Computer Science Pennsylvania State University University Park PA USA

Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With the presence of complex cores in current day embedded system-on-chip devices, the problem of complete system level power estimation is gaining significance. Transaction level models for SoCs are gaining increasing attention with emerging architectural modeling standards like systemC. In this paper we present a methodology for performing system power estimation for different scenarios or applications being executed on these transaction level models. We describe techniques and a setup for transaction level power characterization, and an approach to augment systemC transaction level models to perform transaction level power estimation. We also present experimental results to validate the accuracy and speed of our approach.

关键词： Power system modeling Integrated circuit modeling Energy consumption Frequency Bandwidth Embedded software Computer architecture State estimation Computer science system-on-a-chip

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Enhanced code density of embedded CISC processors with echo technology

Enhanced code density of embedded CISC processors with echo ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Mauricio Breternitz Herbert Hum Ramesh Peri Jay Pickett Youfeng Wu INTEL Research Laboratory Santa Clara CA USA Low Power Microprocessor Laboratory INTEL Research Laboratory Santa Clara CA USA Compiler Laboratory INTEL Research Laboratory Santa Clara CA USA

Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even at the cost of significant performance loss. In this paper, we develop an algorithm that utilizes a set of novel variable length Echo instructions and evaluate its effectiveness for IA32 binaries. Our experiments show that IA32 processor equipped with Echo instructions is capable of achieving a similar code density as the THUMB extension in the ARM instruction set with significantly lower performance penalty.

关键词： Thumb Performance loss Reduced instruction set computing Program processors Costs Design optimization Optimizing compilers Embedded system Permission Microprocessors

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Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design

Service dependency graph: an efficient model for hardware/so...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Ahmed Amine Jerraya Frederic Rousseau Aimen Bouchhima Mohamed-wassim Youssef Arnaud Grasset Wander Cesario Lobna Kriaa Adriano Sarmento SLS Group TIMA Laboratory Grenoble France

Complex systems-on-chip are designed by interconnecting pre-designed hardware (HW) and software (SW) components. During the design cycle, a global model of the SoC may be composed of HW and SW models at different abstraction levels. Designing HW/SW interfaces to interconnect SoC components is a source of design bottlenecks. This paper describes a service-based model enabling systematic design and co-simulation of HW/SW interfaces for SoC design. This model, called Service dependency graph (SDG) allows modeling of complex and application-specific interfaces. We present also a model generator that can automatically build HW/SW interfaces based on service and resource requirements described by the SDG. This approach has been applied successfully on the design of an MPEG-4 encoder. Additionally the SDG seems to be an excellent intermediate representation for the design automation of HW/SW interfaces.

关键词： hardware Middleware Costs Design automation Time to market Laboratories Laser sintering MPEG 4 Standard Computer aided instruction Computer interfaces

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FlexPath NP: a network processor concept with application-driven flexible processing paths

FlexPath NP: a network processor concept with application-dr...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Andreas Herkersdorf Thomas Wild Rainer Ohlendorf Munich University of Technology Munich Germany

In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP) application sub-functions onto both SW programmable processor (CPU) resources and (re-)configurable HW building blocks, such that different packet flows are forwarded via different, optimized processing paths through the NP. Packets with well understood, relatively simple processing requirements may even bypass the central CPU complex (AutoRoute). In consequence, CPU processing resources are more effectively used and the overall NP performance and throughput are improved compared to conventional NP architectures. We present analytical performance estimations to quantify the performance advantage of FlexPath (expressed as available CPU instructions for each packet traversing the CPUs) and introduce a platform-based system on Programmable Chip (SoPC) based architecture which implements the FlexPath NP concept.

关键词： hardware Throughput Very large scale integration Virtual private networks DSL Computer architecture Permission Performance analysis Coprocessors Network interfaces

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