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What will system level design be when it grows up?

What will system level design be when it grows up?

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Patrick Lysaght Peter Marwedel Mike Muller Daniel Gajski David Goodwin Jeff Welser Grant Martin Xilinx Research University of Dortmund Germany ARM UK UC Irvine Tensilica IBM

We have seen a growing new interest in Electronic system Level (ESL) architectures, design methods, tools and implementation fabrics in the last few years. But the picture of what types and approaches to building embedded systems will become the most widely-accepted norms in the future remains fuzzy at best. Everyone want to know where systems and system design is going "when it grows up", if it ever "grows up". Some of the key questions that need to be answered include which applications will be key system drivers, what SW&HW architectures will suit best, how programmable and configurable will they be, will systems designers need to deal with physical implementation issues or will that be hidden behind fabric abstractions and programming models, and what will those abstractions and models be? Moreover, will these abstractions stabilize and be still useful as the underlying technology keeps developing at high *** panel consists of proponents of a number of alternative visions for where we will end up, and how we will get there.

关键词： system-level design Fabrics Design methodology Buildings Embedded system Fuzzy systems Cities and towns

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Novel architecture for loop acceleration: a case study

Novel architecture for loop acceleration: a case study

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Sri Parameswaran Newton Cheung Seng Lin Shee School of Computer Science and Engineering University of New South Wales Sydney Australia National Information and Communications Technology Australia NICTA Sydney Australia VaST Systems Technology Corporation Sydney Australia

In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this architecture. To illustrate the advantages of this approach, we investigate a JPEG encoding algorithm and accelerate one of its loop by implementing it in a coprocessor. We contrast the acceleration by implementing the critical segment as two different coprocessors and a set of customized instructions. The two different coprocessor approaches are: a high-level synthesis (HLS) approach; and a custom coprocessor approach. The HLS approach provides a faster method of generating coprocessors. We show that a loop performance improvement of 2.57x is achieved using the custom coprocessor approach, compared to 1.58x for the HLS approach and 1.33x for the customized instruction approach compared with just the main processor. Respective energy savings within the loop are 57%, 28% and 19%.

关键词： Acceleration Coprocessors Application specific processors Australia High level synthesis Delay Parallel processing Pipeline processing Computer architecture Energy consumption

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Energy-efficient address translation for virtual memory support in low-power and real-time embedded processors

Energy-efficient address translation for virtual memory supp...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Peter Petrov Xiangrong Zhou University of Maryland College Park USA

In this paper we present an application-driven address translation scheme for low-power and real-time embedded processors with virtual memory support. The power inefficiency and nondeterministic execution times of address-translation mechanisms have been major barriers in adopting and utilizing the benefits of virtual memory in embedded processors with low-power and real-time constraints. To address this problem, we propose a novel, Customizable Translation Table (CTT) organization, where application knowledge regarding the virtual memory footprint is used in order to eliminate conflicts in the hardware translation buffer and, thus, achieve tag-free address translation lookups. The set of virtual pages is partitioned into groups, such that for each group only a few of the least significant bits are used as an index to obtain the physical page number. We outline an efficient compile-time algorithm for identifying these groups and allocate their translation entries optimally into the CTT. The proposed methodology relies on the combined efforts of compiler, operating system, and hardware architecture to achieve a significant power reduction. The experiments that we have performed on a set of embedded applications show power reductions in the range of 55% to 80% compared to a general- purpose Translation Lookaside Buffer (TLB).

关键词： Energy efficiency hardware Virtual private networks Educational institutions Energy consumption Partitioning algorithms Operating systems Embedded system Memory management Kernel

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Power optimization for universal hash function data path using divide-and-concatenate technique

Power optimization for universal hash function data path usi...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Ramesh Karri Bo Yang Department of Electrical and Computer Engineering Polytechnic University Brooklyn NY USA

We present an architecture level low power design technique called divide-and-concatenate for universal hash functions based on the following observations: (i) the power consumption of a w-bit array multiplier and associated universal hash data path decreases as O(w4) if its clock rate remains constant. (ii) two universal hash functions are equivalent if they have the same collision probability property. In the proposed approach we divide a w-bit data path (with collision probability 2-w) into two/four w/2-bit data paths (each with collision probability 2-w/2) and concatenate their results to construct an equivalent w-bit data path (with a collision probability 2-w). A popular low power technique that uses parallel data paths saves 62.10% dynamic power consumption incurring 102% area overhead. In contrast, the divide-and-concatenate technique saves 55.44% dynamic power consumption with only 16% area overhead.

关键词： hardware Energy consumption Clocks Design optimization Computer architecture Authentication Iterative algorithms Power system reliability Arithmetic Logic design

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Highly flexible multi-mode system synthesis

Highly flexible multi-mode system synthesis

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international conference on hardware/software codesign and system synthesis (CODES)

作者： John Lach Vinu Vijay Kumar Texas Instruments Inc. Stafford TX USA Department of Electrical & Computer Engineering University of Virginia Charlottesville VA USA

Multi-mode systems have emerged as an area- and power-efficient approach to implementing multiple time-wise mutually exclusive algorithms and applications in a single hardware space. These systems have limited flexibility and temporal separation between modes is achieved by changing only the dataflow between components. This paper presents a synthesis methodology for integrating flexible components and controllers into primarily fixed logic multi-mode systems thereby increasing their overall flexibility and efficiency. The components are built using a technique called small-scale reconfigurability that provides the necessary flexibility without the penalties associated with general-purpose reconfigurable logic. The reconfiguration latency is small enabling both inter-mode and intra-mode reconfiguration of components. Datapath and controller area and power consumption are reduced beyond what is provided in current multi-mode systems using this methodology, without sacrificing performance. The results show an average 7% reduction in datapath component area, 26% reduction in register area, 36% reduction in interconnect MUX cost, and a 68% reduction in the number of controller signals for a set of benchmark 32-bit signal processing applications. There is also an average 38% increase in component utilization.

关键词： Reconfigurable logic Signal processing Signal processing algorithms hardware Control system synthesis Delay Control systems Energy consumption Power system interconnection Costs

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Satisfying real-time constraints with custom instructions

Satisfying real-time constraints with custom instructions

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Tulika Mitra Pan Yu School of Computing National University of Singapore Singapore

Instruction-set extensible processors allow an existing processor core to be extended with application-specific custom instructions. In this paper, we explore a novel application of instruction-set extensions to meet timing constraints in real-time embedded systems. In order to satisfy real-time constraints, the worst-case execution time (WCET) of a task should be reduced as opposed to its average-case execution time. Unfortunately, existing custom instruction selection techniques based on average-case profile information may not reduce a task's WCET. We first develop an Integer Linear Programming (ILP) formulation to choose optimal instruction-set extensions for reducing the WCET. However, ILP solutions for this problem are often too expensive to compute. Therefore, we also propose an efficient and scalable heuristic that obtains quite close to the optimal results. Experiment results indicate that suitable choice of custom instructions can reduce the WCET of our benchmark programs by as much as 42% (23.5% on an average).

关键词： Real time systems Embedded system Frequency Computer aided instruction Permission Processor scheduling Clocks Timing Integer linear programming Algorithm design and analysis

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CRAMES: compressed RAM for embedded systems

CRAMES: compressed RAM for embedded systems

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Haris Lekatsas Robert P. Dick Srimat Chakradhar Lei Yang Northwestern University Evanston IL USA NEC Laboratories of America Inc. Princeton NJ USA

Memory is a scarce resource in many embedded systems. Increasing memory often increases packaging and cooling costs, size, and energy consumption. This paper presents CRAMES, an efficient software-based RAM compression technique for embedded systems. The goal of CRAMES is to dramatically increase effective memory capacity without hardware design changes, while maintaining high performance and low energy consumption. To achieve this goal, CRAMES takes advantage of an operating system's virtual memory infrastructure by storing swapped-out pages in compressed format. It dynamically adjusts the size of the compressed RAM area, protecting applications capable of running without it from performance or energy consumption penalties. In addition to compressing working data sets, CRAMES also enables efficient in-RAM filesystem compression, thereby further increasing RAM capacity. CRAMES was implemented as a loadable module for the Linux kernel and evaluated on a battery-powered embedded system. Experimental results indicate that CRAMES is capable of doubling the amount of RAM available to applications. Execution time and energy consumption for a broad range of examples increase only slightly, by averages of 0.35% and 4.79%. In addition, this work identifies the software-based compression algorithms that are most appropriate for low-power embedded systems.

关键词： Embedded system Read-write memory Random access memory Energy consumption Packaging Cooling Costs hardware Protection Linux

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Shift buffering technique for automatic code synthesis from synchronous dataflow graphs

Shift buffering technique for automatic code synthesis from ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Nikil Dutt Soonhoi Ha Hyunok Oh CECS University of California Irvine CA USA School of EECS Seoul National University Seoul South Korea

This paper proposes a new efficient buffer management technique called shift buffering for automatic code synthesis from synchronous dataflow graphs (SDF). Two previous buffer management methods, linear buffering and modulo (or circular) buffering, assume that samples are queued in the arc buffers in the arrival order and are accessed by moving the buffer indices. But both methods have significant overhead for general multi-rate systems: the linear buffering method requires large size buffers and the modulo buffering method needs run-time overhead of buffer index computation. The proposed shift buffering method shifts samples rather than moving buffer indices. We develop optimal shift buffering algorithms to minimize the number of shifted samples. Our experimental results show that the proposed algorithm saves up to 90% of performance overhead while requiring the same amount of buffer memory as modulo buffering. Considering the sample copy overhead, shift buffering is applicable when memory size is more crucial than performance overhead, and the shifting overhead is less than the modulo addressing overhead. Another advantage of the shift buffering technique is that it supports the library code written with the linear buffering assumption, which is practically more important.

关键词： Signal processing algorithms Runtime Application software Embedded system software libraries software design Pipelines Signal design Digital signal processing Signal synthesis

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Future wireless convergence platforms 05

Future wireless convergence platforms

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Mayan Moudgill Michael Schulte Stamatis Vassiliadis Daniel Iancu Gary Nacer Michael Samori Sanjay Jintukar Stuart Stanley Tanuj Raja John Glossner Sandbridge Technologies Inc. White Plains NY USA Sandbridge Technologies Inc. White Plains NY

ISBN: (纸本)9781595931610

As wireless platforms converge to multimedia systems, architectures must converge to support voice, data, and video applications. From a processor architecture perspective, support for signal processing (both audio and video), control code, and Java execution will be required in a convergent device. Traditionally, wireless communications systems have been implemented in hardware. Convergent devices must be able to roam seamlessly across multiple communications systems. To avoid excessive hardware costs, a software Defined Radio (SDR) approach offers a programmable and dynamically reconfigurable method of reusing hardware to implement physical layer processing. In this paper, we discuss trends in wireless platforms which are inherently convergence platforms. We also present the Sandbridge state-of-the-art example platform that supports both communications and multimedia applications processing. The architecture efficiently executes Java, Digital Signal Processing (DSP), and control code. Architectural features that reduce power dissipation and enable real-time processing are described. All of the communications and multimedia processing is executed completely in software without specialized hardware support. The processor is programmed in C with supercomputer-class compiler support for automatic vectorization, multithreading, and DSP semantic analysis.

关键词： Convergence hardware Digital signal processing Computer architecture Communication system control Java Multimedia communication Multimedia systems Video signal processing Wireless communication

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A cycle-accurate compilation algorithm for custom pipelined datapaths

A cycle-accurate compilation algorithm for custom pipelined ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Daniel Gajski Mehrdad Reshadi Center for Embedded Computer Systems CECS University of California Irvine CA USA

Traditional high level synthesis (HLS) techniques generate a datapath and controller for a given behavioral description. The growing wiring cost and delay of today technologies require aggressive optimizations, such as interconnect pipelining, that cannot be done after generating the datapath and without invalidating the schedule. On the other hand, the increasing manufacturing complexities demand approaches that favor design for manufacturability (DFM).To address these problems we propose an approach in which the datapath of the architecture is fully allocated before scheduling and binding. We compile a C program directly to the datapath and generate the controller. We can support the entire ANSI C syntax because the datapath can be as complex as the datapath of a processor. Since there is no instruction abstraction in this architecture we call it No-Instruction-Set-Computer (NISC). As the first step towards realization of a NISC-based design flow, we present an algorithm that maps an application on a given datapath by performing scheduling and binding simultaneously. With this algorithm, we achieved up to 70% speedup on a NISC with a datapath similar to that of MIPS, compared to a MIPS gcc compiler. It also efficiently handles different datapath features such as pipelining, forwarding and multi-cycle units.

关键词： Job shop scheduling High level synthesis Pipeline processing Manufacturing Processor scheduling Wiring Cost function Delay Algorithm design and analysis Scheduling algorithm

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