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A cycle-accurate compilation algorithm for custom pipelined datapaths

A cycle-accurate compilation algorithm for custom pipelined ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Daniel Gajski Mehrdad Reshadi Center for Embedded Computer Systems CECS University of California Irvine CA USA

Traditional high level synthesis (HLS) techniques generate a datapath and controller for a given behavioral description. The growing wiring cost and delay of today technologies require aggressive optimizations, such as interconnect pipelining, that cannot be done after generating the datapath and without invalidating the schedule. On the other hand, the increasing manufacturing complexities demand approaches that favor design for manufacturability (DFM).To address these problems we propose an approach in which the datapath of the architecture is fully allocated before scheduling and binding. We compile a C program directly to the datapath and generate the controller. We can support the entire ANSI C syntax because the datapath can be as complex as the datapath of a processor. Since there is no instruction abstraction in this architecture we call it No-Instruction-Set-Computer (NISC). As the first step towards realization of a NISC-based design flow, we present an algorithm that maps an application on a given datapath by performing scheduling and binding simultaneously. With this algorithm, we achieved up to 70% speedup on a NISC with a datapath similar to that of MIPS, compared to a MIPS gcc compiler. It also efficiently handles different datapath features such as pipelining, forwarding and multi-cycle units.

关键词： Job shop scheduling High level synthesis Pipeline processing Manufacturing Processor scheduling Wiring Cost function Delay Algorithm design and analysis Scheduling algorithm

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Anomalous path detection with hardware support

Anomalous path detection with hardware support

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CASES 2005: international conference on Compilers, Architecture, and synthesis for Embedded systems

作者： Zhang, Tao Zhuang, Xiaotong Pande, Santosh Lee, Wenke College of Computing Georgia Institute of Technology Atlanta GA 30332-0280 United States

ISBN: (纸本)159593149X

Embedded systems are being deployed as a part of critical infrastructures and are vulnerable to malicious attacks due to internet accessibility. Intrusion detection systems have been proposed to protect computer systems from unauthorized penetration. Detecting an attack early on pays off since further damage is avoided and in some cases, resilient recovery could be adopted. This is especially important for embedded systems deployed in critical infrastructures such as Power Grids etc. where a timely intervention could save catastrophes. An intrusion detection system monitors dynamic program behavior against normal program behavior and raises an alert when an anomaly is detected. The normal behavior is learnt by the system through training and profiling. However, all current intrusion detection systems are purely software based and thus suffer from large performance degradation due to constant monitoring operations inserted in application code. Due to the potential performance overheads, software based solutions cannot monitor program behavior at a very fine level of granularity, thus leaving potential security holes as shown in the literature. Another important drawback of such methods is that they are unable to detect intrusions in near real time and the time lag could prove disastrous in real time embedded systems. In this paper, we propose a hardware-based approach to verify program execution paths of target applications dynamically and to detect anomalous executions. With hardware support, our approach offers multiple advantages over software based solutions including minor performance degradation, much stronger detection capability (a larger variety of attacks get detected) and zero-latency reaction upon an anomaly for near real time detection and thus much better security. Copyright 2005 acm.

关键词： Embedded systems

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Memory access optimizations in instruction-set simulators

Memory access optimizations in instruction-set simulators

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Prabhat Mishra Mehrdad Reshadi Center for Embedded Computer Systems (CECS) University of California Irvine Irvine CA USA Computer and Information Science and Engineering University of Florida Gainesville FL USA

Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simulators are widely used in embedded systems design. One of the key performance bottlenecks in interpretive simulation is the instruction and data memory access translation between host and target machines. The simulators must maintain and update the status of the simulated processor including memory and register values. A major challenge in the simulation is to efficiently map the target address space to the host address space. This paper presents two optimization techniques that aggressively utilize the spatial locality of the instruction and data accesses in interpretive simulation: signature based address mapping for optimizing general memory accesses; and incremental instruction fetch for optimizing instruction accesses. To demonstrate the utility of this approach we applied these techniques on SimpleScalar simulator, and obtained up to 30% performance improvement. Our techniques complement the recently proposed optimizations (JIT-CCS [1] and IS-CS [2]) and further improve the performance (up to 89%) on ARM7 and Sparc processors.

关键词： Decoding Computational modeling Runtime Computer aided instruction Embedded computing Embedded system Permission Computer simulation Information science Process design

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An efficient direct mapped instruction cache for application-specific embedded systems

An efficient direct mapped instruction cache for application...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Chuanjun Zhang Computer Science and Electrical Engineering Department University of Missouri Kansas City Kansas City MO USA

Caches may consume half of a microprocessor's total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing cache power consumption and reducing cache misses are important to reduce total energy consumption of embedded systems. Direct mapped caches consume much less power than that of same sized set associative caches but with a poor hit rate on average. Through experiments, we observe that memory space of direct mapped instruction caches is not used efficiently in most embedded applications. We design an efficient cache - a configurable instruction cache that can be tuned to utilize the cache sets efficiently for a particular application such that cache memory is exploited more efficiently by index remapping. Experiments on 11 benchmarks drawn from Mediabench show that the efficient cache achieves almost the same miss rate as a conventional two-way set associative cache on average and with total memory-access energy savings of 30% compared with a conventional two-way set associative cache.

关键词： Embedded system Energy consumption Delta modulation Cache memory Algorithm design and analysis Cities and towns Computer science Clocks Frequency Application specific processors

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Designing real-time H.264 decoders with dataflow architectures

Designing real-time H.264 decoders with dataflow architectur...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Suleyman Sair Youngsoo Kim Department of Electrical and Computer Engineering NC State University USA

High performance microprocessors are designed with general-purpose applications in mind. When it comes to embedded applications, these architectures typically perform control-intensive tasks in a system-on-Chip (SoC) design. But they are significantly inefficient for data-intensive tasks such as video encoding/decoding. Although configurable processors fill this gap by complementing the existing functional units with instruction extensions, their performance lags behind the needs of real-time embedded tasks. In this paper, we evaluate the performance potential of a dataflow processor for H.264 video decoding. We first profile the H.264 application to capture the amount of data traffic among modules. We use this information to guide the placement of H.264 modules in the WaveScalar dataflow architecture. A simulated annealing based placement algorithm produces the final placement aiming to optimize the communication costs between the modules in the dataflow architecture. In addition to outperforming contemporary embedded and customized processors, our simulated annealing guided design shows a speedup of 13% in execution time over the original WaveScalar architecture. With our dataflow design methodology, emerging embedded applications requiring several GOPS to meet real-time constraints can be drafted within a reasonable amount of design time.

关键词： Decoding Computer architecture Design methodology Application software Acceleration Encoding Simulated annealing Permission Microprocessors Control systems

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Improving superword level parallelism support in modern compilers

Improving superword level parallelism support in modern comp...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Manuel Prieto Luis Pinuel F. Catthoor Francisco Tirado Christian Tenllado Departmento Arquitectura de Computadores y Automática Universidad Complutense de Madrid Madrid Spain Micro Electronic Center IMEC Inter University Leuven Belgium

Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology do not allow for an efficient exploitation of the inherent data parallelism available in many signal processing and multimedia applications. In this paper, we have explored the automatic vectorization of embedded applications. In particular, we have focused on algorithms in which the same computations are applied over a set of signals that are being processed simultaneously. Usually this set of signals is represented as a 2D array in which each row is an input signal that has to be filtered in some way. A motivating example, inspired by VoIP processing, illustrates that state-of-the-art vectorizing compilers inefficiently exploit the data parallelism inherent to this kind of applications. One of the main reasons behind this, is that they present inner loops that carry all the dependencies and external loops with strided memory *** propose a modification of the Superword Level Parallelism (SLP) compiler, proposed in [9], that tries to overcome these problems. Experimental results show that our approach clearly outperforms commercial compilers.

关键词： Signal processing algorithms Parallel processing Signal processing Multimedia systems Embedded system Finite impulse response filter Systolic arrays Permission Pervasive computing Microelectronics

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Aggregating processor free time for energy reduction

Aggregating processor free time for energy reduction

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Alex Nicolau Nikil Dutt Eugene Earlie Aviral Shrivastava Center for Embedded Computer Systems School of Information and Computer Science University of California Irvine CA USA Strategic CAD Laboratories Intel Corporation Hudson MA USA

Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the processor stalls, waiting for data from the memory. Processor stall can be used to increase the throughput by temporarily switching to a different thread of execution, or reduce the power and energy consumption by temporarily switching the processor to low-power mode. However, any such technique has a performance overhead in terms of switching time. Even though over the execution of an application the processor is stalled for a considerable amount of time, each stall duration is too small to profitably perform any state switch. In this paper, we present code transformations to aggregate processor free time. Our experiments on the Intel XScale and Stream kernels show that up to 50,000 processor cycles can be aggregated, and used to profitably switch the processor to low-power mode. We further show that our code transformations can switch the processor to low-power mode for up to 75% of kernel runtime, achieving up to 18% of processor energy savings on multimedia applications. Our technique requires minimal architectural modifications and incurs negligible ( < 1%) performance loss.

关键词： Switches Embedded computing Application software Embedded system Algorithm design and analysis Energy consumption Kernel Delay Permission Computer science

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Enhancing security through hardware-assisted run-time validation of program data properties

Enhancing security through hardware-assisted run-time valida...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Anand Raghunathan Niraj K. Jha Srivaths Ravi Divya Arora Department of Electrical Engineering Princeton University Princeton NJ USA NEC Laboratories of America Inc. Princeton NJ USA

The growing number of information security breaches in electronic and computing systems calls for new design paradigms that consider security as a primary design objective. This is particularly relevant in the embedded domain, where the security solution should be customized to the needs of the target system, while considering other design objectives such as cost, performance, and power. Due to the increasing complexity and shrinking design cycles of embedded software, most embedded systems present a host of software vulnerabilities that can be exploited by security attacks. Many attacks are initiated by causing a violation in the properties of data ( e.g., integrity, privacy, access control rules, etc.) associated with a "trusted" program that is executing on the system, leading to a range of undesirable *** this work, we develop a general framework that provides security assurance against a wide class of security attacks. Our work is based on the observation that a program's permissible behaviorwith respect to data accesses can be characterized by certain properties. We present a hardware/software approach wherein such properties can be encoded as data attributes and enforced as security policies during program execution. These policies may be application-specific (e.g., access control for certain data structures), compiler-generated (e.g., enforcing that variables are accessed only within their scope), or universally applicable to all programs (e.g., disallowing writes to unallocated memory). We show how an embedded system architecture can support such policies by (i) enhancing the memory hierarchy to represent the attributes of each datum as security tags that are linked to it through its lifetime, and (ii) adding a configurable hardware checker that interprets the semantics of the tags and enforces the desired security policies. We evaluated the effectiveness of the proposed architecture in enforcing various security policies for several embedded benchma

关键词： Data security Runtime Information security Power system security Embedded software Embedded system Access control hardware Costs Data privacy

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Blue matter on blue gene/L: massively parallel computation for biomolecular simulation

Blue matter on blue gene/L: massively parallel computation f...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Frank Suits Maria Eleftheriou Mark Giampapa Aleksandr Rayshubskiy Blake Fitch Michael C. Pitman T.J. Christopher Ward Robert S. Germain IBM Thomas J. Watson Research Center Yorktown Heights NY USA IBM Hursley Park Hursley UK

This paper provides an overview of the Blue Matter application development effort within the Blue Gene project that supports our scientific simulation efforts in the areas of protein folding and membrane-protein systems. The design philosophy of the Blue Gene/L architecture relies on large numbers of power efficient nodes (whose technology is derived from the world of embedded microprocessors) to enable packing of many such nodes into a small volume to achieve high performance. In order for an application to exploit the potential of this architecture, the application must scale well to large node counts. Because the scientific goals of the project entail simulating very long time-scales, up to microseconds, strong scaling of a fixed size problem to these large node counts is a requirement. In pursuit of this objective we have considered a variety of parallel decompositions and explored ways to exploit and map algorithms onto the two primary high performance interconnects provided by the Blue Gene architecture, the 3D-torus network and the collective network. Our current version of the application continues to speed up through 4096 nodes and is being used for studies of a protein/lipid system (for which some results have already been published) and for protein folding/unfolding simulations.

关键词： Concurrent computing Computational modeling Biological system modeling Proteins hardware Bonding forces Boundary conditions Microprocessors Permission Supercomputers

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hardware and software architectures for the CELL processor

Hardware and software architectures for the CELL processor

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Michael Day Peter Hofstee Cell Chief Scientist and Cell Synergistic Processor Chief Architect IBM Systems and Technology Group Austin TX USA Cell Chief Software Architect and Distinguished Engineer IBM Systems and Technology Group Austin TX USA

The Cell processor is a first instance of a new family of processors intended for the broadband era. The processors will find early use in game systems (PlayStation3TM), a variety of other consumer electronics applications, a wide variety of embedded applications, and various forms of computational accelerators. Cell is a non-homogeneous multi-core processor, with one POWER processor core (two threads) dedicated to the operating system and other control functions, and eight synergistic processors optimized for compute-intensive *** addresses two of the main limiters to microprocessor performance: increased memory latency, and performance limitations induced by system power limits. Memory latency is addressed by introducing another software-managed level of private "local" memory, in between the private registers and shared system memory. Data is transferred between this local memory and shared memory with asynchronous cache coherent DMA commands, and synergistic processor load and store commands access the local store only. This organization of memory makes it possible for the Cell processor to have over 100 memory transactions in flight at the same time, more than enough to cover memory latency. Power limitations are addressed by two main mechanisms; a non-homogeneous multi-core organization, and an ultra high-frequency design that allows the chip to be operated at 3.2GHz at low *** Cell processor supports many of today's programming models by introducing the concept of heterogeneous tasks or threads. Both Power processor and SPE based threads can be managed by the operating system and effectively utilized by applications starting with the relatively straightforward function offload model to the more complex single source heterogeneous parallel programming model. Cell achieves between one and two orders of magnitude of performance advantage over conventional single-core processors on compute-intensive (32-bit) applications, by permitting progr

关键词： hardware software architecture Yarn Delay Power system modeling Application software Operating systems Computer applications Registers Games

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