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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

共 1035 条记录，以下是781-790 订阅

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Proceedings. Third acm & IEEE international conference on Formal Methods and Models for Co-Design (IEEE Cat. No. 05EX1093)

Proceedings. Third ACM & IEEE International Conference on Fo...

引用

acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

The following topics are dealt with: hardware synthesis; hardware languages; hardware semantics; software verification; system-level verification; model checking; microarchitectural specification; microarchitectural v...

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The design of a smart imaging core for automotive and consumer applications: a case study 05

The design of a smart imaging core for automotive and consum...

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Proceedings of the 3rd IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Wido Kruijtzer Winfried Gehrke Victor Reyes Ghiath Alkadi Thomas Hinz Jorn Jöchalsky Bruno Steux Philips Research The Netherlands Philips Semiconductors Hamburg Germany University of Las Palmas GC Spain University of Hannover Germany École des Mines de Paris France

ISBN: (纸本)9781595931610

This paper describes the design of a low-cost, low-power smart imaging core that can be embedded in cameras. The core integrates an ARM 9 processor, a camera interface and two specific hardware blocks for image processing: a smart imaging coprocessor and an enhanced motion estimator. Both coprocessors have been designed using high-level synthesis tools taking the C programming language as a starting point. The resulting RTL code of each coprocessor has been synthesized and verified on an FPGA board. Two automotive and two mobile smart imaging applications are mapped onto the resulting smart imaging core. This mapping process of the original C++ applications onto the smart imaging core is also presented in this paper.

关键词： system level design image processing

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Proceedings. Third acm & IEEE international conference on Formal Methods and Models for Co-Design (IEEE Cat. No. 05EX1093) 05

Proceedings. Third ACM & IEEE International Conference on Fo...

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Proceedings of the 2nd acm/IEEE international conference on Formal Methods and Models for Co-Design

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SOMA: a tool for synthesizing and optimizing memory accesses in ASICs 05

SOMA: a tool for synthesizing and optimizing memory accesses...

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Proceedings of the 3rd IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Girish Venkataramani Tiberiu Chelcea Seth Copen Goldstein Tobias Bjerregaard Carnegie Mellon University Pittsburgh PA TU Denmark Lyngby Denmark

ISBN: (纸本)9781595931610

Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOMA, a synthesis framework for constructing Memory Access Network (MAN) architectures that inherently enforce memory consistency in the presence of dynamic memory access dependencies. A fundamental bottleneck in any such network is arbitrating between concurrent accesses to a shared memory resource. To alleviate this bottleneck, SOMA uses an application-specific concurrency analysis technique to predict the dynamic memory parallelism profile of the application. This is then used to customize the MAN architecture. Depending on the parallelism profile, the MAN may be optimized for latency, throughput or both. The optimized MAN is automatically synthesized into gate-level structural Verilog using a flexible library of network building blocks. SOMA has been successfully integrated into an automated C-to-hardware synthesis flow, which generates standard cell circuits from unrestricted ANSI-C programs. Post-layout experiments demonstrate that application specific MAN construction significantly improves power and performance.

关键词： high-level synthesis memory synthesis

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CRAMES: compressed RAM for embedded systems 05

CRAMES: compressed RAM for embedded systems

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Proceedings of the 3rd IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Lei Yang Robert P. Dick Haris Lekatsas Srimat Chakradhar Northwestern University Evanston IL NEC Laboratories America Princeton NJ

ISBN: (纸本)9781595931610

Memory is a scarce resource in many embedded systems. Increasing memory often increases packaging and cooling costs, size, and energy consumption. This paper presents CRAMES, an efficient software-based RAM compression technique for embedded systems. The goal of CRAMES is to dramatically increase effective memory capacity without hardware design changes, while maintaining high performance and low energy consumption. To achieve this goal, CRAMES takes advantage of an operating system's virtual memory infrastructure by storing swapped-out pages in compressed format. It dynamically adjusts the size of the compressed RAM area, protecting applications capable of running without it from performance or energy consumption penalties. In addition to compressing working data sets, CRAMES also enables efficient in-RAM filesystem compression, thereby further increasing RAM capacity. CRAMES was implemented as a loadable module for the Linux kernel and evaluated on a battery-powered embedded system. Experimental results indicate that CRAMES is capable of doubling the amount of RAM available to applications. Execution time and energy consumption for a broad range of examples increase only slightly, by averages of 0.35% and 4.79%. In addition, this work identifies the software-based compression algorithms that are most appropriate for low-power embedded systems.

关键词： memory embedded system compression

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FlexPath NP: a network processor concept with application-driven flexible processing paths 05

FlexPath NP: a network processor concept with application-dr...

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Proceedings of the 3rd IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Rainer Ohlendorf Andreas Herkersdorf Thomas Wild Munich University of Technology Munich Germany

ISBN: (纸本)9781595931610

In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP) application sub-functions onto both SW programmable processor (CPU) resources and (re-)configurable HW building blocks, such that different packet flows are forwarded via different, optimized processing paths through the NP. Packets with well understood, relatively simple processing requirements may even bypass the central CPU complex (AutoRoute). In consequence, CPU processing resources are more effectively used and the overall NP performance and throughput are improved compared to conventional NP architectures. We present analytical performance estimations to quantify the performance advantage of FlexPath (expressed as available CPU instructions for each packet traversing the CPUs) and introduce a platform-based system on Programmable Chip (SoPC) based architecture which implements the FlexPath NP concept.

关键词： hardware accelerators application-specific architectures network processors dynamically reconfigurable processors IP networking

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High-level synthesis for large bit-width multipliers on FPGAs: a case study 05

High-level synthesis for large bit-width multipliers on FPGA...

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Proceedings of the 3rd IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Gang Quan James P. Davis Siddhaveerasharan Devarkal Duncan A. Buell University of South Carolina Columbia SC

ISBN: (纸本)9781595931610

In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are required for cryptography and error correction circuits for more secure and reliable transmissions over highly insecure and/or noisy channels in networking and multimedia applications. The design space for these circuits is very large when integer multiplication on large operands is carried out hierarchically. In this paper, we explore automated synthesis of high bit-width unsigned integer multiplier circuits by defining and validating an estimator function used in search and analysis of the design space of such circuits. We focus on analysis of a hybrid hierarchical multiplier scheme that combines the throughput advantages of parallel multipliers and the resource cost-effectiveness of serial ones. We present an analytical model that rapidly predicts timing and resource usage for selected model candidates. We evaluate the estimator model in the design of a practical application, a 256-bit elliptic curve adder implemented on a Xilinx FPGA fabric. We show that our estimator allows implementation of fast, efficient circuits, where resultant designs provide order-of-magnitude performance improvements when compared with that of software implementations on a high performance computing platform.

关键词： reconfigurable computing large-scale integer multipliers FPGA devices high level synthesis design exploration

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ICCAD-2005 international conference on Computer Aided Design (IEEE Cat. No. 05CH37700)

ICCAD-2005 International Conference on Computer Aided Design...

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IEEE international conference on Computer-Aided Design

The following topics are dealt with: memory and arithmetic optimization; design manufacturing interaction; circuit layout; digital analog and RF test; design for manufacturing; logic synthesis; double-gated devices; network routing and application specific NoC architectures; memory driven codes; arithmetic constructs; buffers and voltage islands; sequential circuit optimization; nanoelectronics; dynamic voltage scaling; biochips and DNA-based nanofabrication; circuit simulation; analog circuit design; power aware system architecture; software optimization; cellular array architectures; variability aware clocking; oscillator analysis; power noise and thermal issues; nanocomputing; extraction and modeling for interconnect structures; system-level variability modeling; high-level synthesis; model order reduction; statistical timing analysis; formal verification; hardware and software design of sensors; formal equivalence checking and system on chip.

关键词： Circuit optimization Digital arithmetic Routing Design methodology Logic design Analog circuits Cellular logic arrays Oscillators Design automation Reduced order systems Detectors

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Model driven engineering for SoC co-design

Model driven engineering for SoC co-design

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Annual IEEE Northeast Workshop on Circuits and systems (NEWCAS)

作者： J. Dekeyser P. Boulet P. Marquet S. Meftali Laboratoire dInformatique Fondamentale de Lille Université des Sciences et Technologies de Lille Villeneuve d'Ascq France

SoC co-design requires to master a lot of different abstraction levels, different simulation techniques, different synthesis tools. Due to the evolution of the technologies, the best one is the one to come. Evolution of an embedded system both hardware and software, is not simple. The business logic has to be kept and the technical aspect has to be thrown. To improve the permanence of system on chip we have to abstract from the technical concerns. Model driven engineering (MDE) proposes a separation of concerns: application and technical concerns. The use of a modeling standard can capitalize system descriptions and improve system evolution and integration. A particular aspect of MDE concerns model transformations and code generation. At this level, the basic model driven architecture pattern involves the definition of a platform-independent model (PIM) and its automated mapping to one or more platform-specific models (PSMs). By defining different PIM and PSM dedicated to embedded systems, we show the benefits of using the MDE approach in system on chip codesign. From UML 2.0 profiles to systemC or VHDL codes, the same model transformation engine is used with different rules expressed in XML.

关键词： Model driven engineering Embedded system system-on-a-chip hardware Embedded software Logic Application software Unified modeling language Engines XML

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Blue matter on blue gene/L: massively parallel computation for biomolecular simulation 05

Blue matter on blue gene/L: massively parallel computation f...

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Proceedings of the 3rd IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Robert S. Germain Blake Fitch Aleksandr Rayshubskiy Maria Eleftheriou Michael C. Pitman Frank Suits Mark Giampapa T.J. Christopher Ward IBM Thomas J. Watson Research Center Yorktown Heights NY IBM Hursley Park Hursley UK

ISBN: (纸本)9781595931610

This paper provides an overview of the Blue Matter application development effort within the Blue Gene project that supports our scientific simulation efforts in the areas of protein folding and membrane-protein systems. The design philosophy of the Blue Gene/L architecture relies on large numbers of power efficient nodes (whose technology is derived from the world of embedded microprocessors) to enable packing of many such nodes into a small volume to achieve high performance. In order for an application to exploit the potential of this architecture, the application must scale well to large node counts. Because the scientific goals of the project entail simulating very long time-scales, up to microseconds, strong scaling of a fixed size problem to these large node counts is a requirement. In pursuit of this objective we have considered a variety of parallel decompositions and explored ways to exploit and map algorithms onto the two primary high performance interconnects provided by the Blue Gene architecture, the 3D-torus network and the collective network. Our current version of the application continues to speed up through 4096 nodes and is being used for studies of a protein/lipid system (for which some results have already been published) and for protein folding/unfolding simulations.

关键词： physical design microfluidics biochip synthesis

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