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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

共 1034 条记录，以下是71-80 订阅

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Work-in-Progress: The RISC-V Instruction Set Architecture Optimization and Fixed-point Math Library Co-design

Work-in-Progress: The RISC-V Instruction Set Architecture Op...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Meng Liu Faculty of Information Technology School of Microelectronics Beijing University of Technology Beijing China

ISBN: (纸本)9781665417242

In the field of IoT, RISC-V as an open-source instruction set shows great application potential. On the one hand, this is due to the low cost brought by the hardware open source trend. On the other hand, the modular instruction set architecture (ISA) design brings agile design ideas, and designers can pay more attention to the collaborative design of key ISA and software libraries. However, by analyzing the underlying mathematical assembly library, we found that the current RISC-V standard instruction set still has room for performance improvement for lightweight control mathematical operations. In this paper, we introduce a set of custom RISC-V ISA designs for fixed-point math libraries and perform performance evaluations to demonstrate the optimization results.

关键词： Performance evaluation software libraries Costs Instruction sets Computer architecture Market research hardware

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Extracting hardware Reconfiguration Models Based on Knowledge synthesis from STEP Files

Extracting Hardware Reconfiguration Models Based on Knowledg...

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conference on Model Driven Engineering Languages and systems Companion (MODELS-C)

作者： Birte Caesar Nico Jansen Maximilian Weigand Alexander Fay Bernhard Rumpe Institute of Automation Technology Helmut-Schmidt-University Hamburg Germany Software Engineering RWTH Aachen University Aachen Germany

Today's industrial manufacturing challenges force manufacturers to optimize and increase the flexibility of their facilities. In practice, this requires analyzing, preparing for adaptation, and adapting brownfield manufacturing systems. The digital twin, a digital representation of a manufacturing system, is a key enabler for efficiency, flexibility, and sustainability. Unfortunately, the analysis and preparation of brownfield systems for adaptation, as well as the creation of digital twins, are challenging and time-consuming tasks. This paper presents an approach to automatically create digital models of systems based on 3D CAD models. To this end, the CAD data, stored as a STEP file, is analyzed to extract relevant information for a subsequent graph analysis, which is used to identify components, their dependencies, and the resulting functional modules. Finally, the gained knowledge is transformed into feature models that can be used as a digital model for configuration selection to support automatic reconfiguration planning of brownfield manufacturing systems. The developed approach is evaluated based on an industrial use case of a soft gripper system.

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Work-in-Progress: Register File Management for PRET Machines

Work-in-Progress: Register File Management for PRET Machines

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Martin Koštál Michal Sojka Czech Technical University in Prague

ISBN: (纸本)9781665417242

PREcision Timed (PRET) machines often use multithreading to achieve high CPU resources utilisation and time-determinism. Multithreading enables sharing most of the pipeline resources between threads, except the register file (RF), which is used to store thread context. Traditional multithreading on PRET machines uses large RF. We propose a register file management (RFM) technique suitable for multithreaded PRET machines, reducing the RF size. Our RFM has software-controlled RF partitions for each thread with support for runtime repartitioning. We evaluate the design on the PRET uRISC processor with a 55% average reduction of FPGA resource utilisation and show performance tradeoff on a selection of TACLeBench benchmarks.

关键词： Radio frequency Runtime Multithreading Instruction sets Static analysis software Real-time systems

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Special Session: Machine Learning for Embedded system Design

Special Session: Machine Learning for Embedded System Design

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Proceedings of the 2023 international conference on hardware/software codesign and system synthesis

作者： Erika Susana Alcorta Lozano Andreas Gerstlauer Chenhui Deng Qi Sun Zhiru Zhang Ceyu Xu Lisa Wu Wills Daniela Sanchez Lopera Wolfgang Ecker Siddharth Garg Jiang Hu Electrical and Computer Engineering The University of Texas at Austin Austin Texas USA Electrical and Computer Engineering Cornell University Ithaca New York USA Eletrical and Computer Engineering Cornell University Ithaca New York USA Computer Science Duke University Durham North Carolina USA Corporate Design Infineon Munich Germany Electrial and Computer Engineering New York University New York New York USA Electrical and Computer Engineering Texas A&M University College Station Texas USA

ISBN: (纸本)9798400702891

Embedded systems are becoming increasingly complex, which has led to a productivity crisis in their design and verification. Although conventional design automation coupled with IP and platform reuse techniques have led to leaps in design productivity improvement, they face fundamental limits given that most design optimization and verification problems remain NP-hard and that reuse of pre-designed IP blocks and platforms inherently limits flexibility and optimality. At the same time, machine learning (ML) has recently made unprecedented advances and created phenomenal impact in various computing applications. In particular, application of ML techniques as a way to extract knowledge and learn from existing design, optimization and verification data has recently seen a lot of excitement and promise at lower physical and integrated circuit levels of abstraction. Using ML has the potential to similarly close the complexity gap in embedded system design, but corresponding ML-based approaches for embedded system optimization and verification at higher levels of abstraction are still at their *** paper presents the current state of the art, along with opportunities and open challenges, in the application of ML methods for embedded system design and optimization. We discuss design and optimization at different levels of abstraction ranging from system-level modeling and optimization and high-level synthesis to RTL and micro-architecture design, bringing together perspectives from different communities in both academia and industry.

关键词： machine learning embedded system design

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Work-in-Progress: Early Power Estimation of CUDA-based CNNs on GPGPUs

Work-in-Progress: Early Power Estimation of CUDA-based CNNs ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Christopher A. Metz Mehran Goli Rolf Drechsler University of Bremen Bremen Germany

ISBN: (纸本)9781665417242

The increasing application of Machine Learning (ML) techniques in the Internet of Things (IoT) devices has led designers to leverage ML accelerators like GPGPUs in such devices. However, choosing the most appropriate accelerator for such IoT devices is very challenging as they commonly should adhere to tight constraints e.g., low power consumption, long battery lifetime, and low cost of the final products. As a consequence, designing such application-specific IoT devices becomes a non-trivial and difficult task. In this paper, we present a novel approach to estimate power consumption of CUDA-based Convolutional Neural Networks (CNNs) on GPGPUs in the design phase. Our approach is able to provide designers with an early prediction of CNNs power consumption up to an absolute error of less than 2% in comparison to the real hardware execution.

关键词： Power demand Costs Estimation Machine learning hardware Batteries Internet of Things

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Physics-aware Differentiable Discrete codesign for Diffractive Optical Neural Networks

Physics-aware Differentiable Discrete Codesign for Diffracti...

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IEEE international conference on Computer-Aided Design

作者： Yingjie Li Ruiyang Chen Weilu Gao Cunxi Yu ECE Department University of Utah Salt Lake City Utah USA

Diffractive optical neural networks (DONNs) have attracted lots of attention as they bring significant advantages in terms of power efficiency, parallelism, and computational speed compared with conventional deep neural networks (DNNs), which have intrinsic limitations when implemented on digital platforms. However, inversely mapping algorithm-trained physical model parameters onto real-world optical devices with discrete values is a non-trivial task as existing optical devices have non-unified discrete levels and non-monotonic properties. This work proposes a novel device-to-system hardware-software codesign framework, which enables efficient physics-aware training of DONNs w.r.t arbitrary experimental measured optical devices across layers. Specifically, Gumbel-Softmax is employed to enable differentiable discrete mapping from real-world device parameters into the forward function of DONNs, where the physical parameters in DONNs can be trained by simply minimizing the loss function of the ML task. The results have demonstrated that our proposed framework offers significant advantages over conventional quantization-based methods, especially with low-precision optical devices. Finally, the proposed algorithm is fully verified with physical experimental optical systems in low-precision settings.

关键词： Integrated optics Training Temperature measurement Optical diffraction Optical design Neural networks Optical computing

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Type-Directed Program synthesis and Constraint Generation for Library Portability 19

Type-Directed Program Synthesis and Constraint Generation fo...

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Proceedings of the international conference on Parallel Architectures and Compilation Techniques

作者： Bruce Collie Philip Ginsbach Michael F.P. O'Boyle School of Informatics University of Edinburgh United Kingdom

ISBN: (纸本)9781728136134

Fast numerical libraries have been a cornerstone of scientific computing for decades, but this comes at a price. Programs may be tied to vendor specific software ecosystems resulting in polluted, non-portable code. As we enter an era of heterogeneous computing, there is an explosion in the number of accelerator libraries required to harness specialized hardware. We need a system that allows developers to exploit ever-changing accelerator libraries, without over-specializing their *** we cannot know the behavior of future libraries ahead of time, this paper develops a scheme that assists developers in matching their code to new libraries, without requiring the source code for these ***, it can recover equivalent code from programs that use existing libraries and automatically port them to new interfaces. It first uses program synthesis to determine the meaning of a library, then maps the synthesized description into generalized constraints which are used to search the program for replacement opportunities to present to the *** applied this approach to existing large applications from the scientific computing and deep learning domains. Using our approach, we show speedups ranging from 1.1× to over 10× on end to end performance when using accelerator libraries.

关键词： code rejuvenation

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Centralized Generic Interfaces in hardware/software Co-design for AI Accelerators 42

Centralized Generic Interfaces in Hardware/Software Co-desig...

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42nd IEEE/acm international conference on software Engineering Workshops, ICSEW 2020

作者： Chae, Dongju Kapoor, Parichay Samsung Electronics Korea Republic of

ISBN: (纸本)9781450379632

A hardware/software co-design for AI accelerators such as Neural Processing Unit (NPU) is essential not only to support the required functionality but also to meet primary goals of improved performance and power efficiency. However, their ever-changing requirements often introduce undesirable development costs. Indeed, it is quite challenging for developers from different backgrounds to efficiently work together to construct a full HW/SW stack to develop AI accelerators. This paper addresses these challenges, and proposes a centralized collaboration methodology for efficient full-stack development, especially targeting NPU HW. The proposal is inspired based on the observations from our experiences, presented later as a case study. As not all of the involved developers have enough knowledge of software engineering, this approach suggests making a central development group (e.g., runtime system software) have a higher priority to organize and devise common interfaces including APIs for each layer in the full-stack. This aims to minimize unnecessary discussions between development groups and hide any minor updates introduced with each new design, reducing the overall development costs and improving the quality of products. More importantly, each development group can focus on their work as much as possible with this approach. © 2020 acm.

关键词： hardware-software codesign

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Automated HW/SW Co-design for Edge AI: State, Challenges and Steps Ahead: Special Session Paper

Automated HW/SW Co-design for Edge AI: State, Challenges and...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Oliver Bringmann Wolfgang Ecker Ingo Feldner Adrian Frischknecht Christoph Gerum Timo Hämäläinen Muhammad Abdullah Hanif Michael J. Klaiber Daniel Mueller-Gritschneder Paul Palomero Bernardo Sebastian Prebeck Muhammad Shafique University of Tübingen Tübingen Germany Infineon Technologies AG Neubiberg Germany Bosch Corporate Research Renningen Germany Tampere University Tampere Finland Technische Universität Wien Austria New York University Abu Dhabi UAE Technical University of Munich Munich Germany New York University Abu Dhabi Abu Dhabi United Arab Emirates

ISBN: (纸本)9781665417242

Gigantic rates of data production in the era of Big Data, Internet of Thing (IoT), and Smart Cyber Physical systems (CPS) pose incessantly escalating demands for massive data processing, storage, and transmission while continuously interacting with the physical world using edge sensors and actuators. For IoT systems, there is now a strong trend to move the intelligence from the cloud to the edge or the extreme edge (known as TinyML). Yet, this shift to edge AI systems requires to design powerful machine learning systems under very strict resource constraints. This poses a difficult design task that needs to take the complete system stack from machine learning algorithm, to model optimization and compression, to software implementation, to hardware platform and ML accelerator design into account. This paper discusses the open research challenges to achieve such a holistic Design Space Exploration for a HW/SW Co-design for Edge AI systems and discusses the current state with three currently developed flows: one design flow for systems with tightly-coupled accelerator architectures based on RISC-V, one approach using loosely-coupled, application-specific accelerators as well as one framework that integrates software and hardware optimization techniques to built efficient Deep Neural Network (DNN) systems.

关键词： Production Tools Market research software hardware Sensor systems Space exploration

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A Runtime system for Finite Element Methods in a Partitioned Global Address Space 20

A Runtime System for Finite Element Methods in a Partitioned...

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17th acm international conference on Computing Frontiers (CF)

作者： Groth, Stefan Grunewald, Daniel Teich, Jurgen Hannig, Frank Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci Hardware Software Codesign Erlangen Germany Fraunhofer ITWM Kaiserslautern Germany

ISBN: (纸本)9781450379564

With approaching exascale performance, applications in the domain of high-performance computing (HPC) have to scale to an ever-increasing amount of compute nodes. The Global Address Space Programming Interface (GASPI) communication API promises to handle this challenge by providing a highly flexible and efficient programming model in a partitioned global address space (PGAS). Suitable applications targeting supercomputers include the domain of mesh-based solvers for partial differential equations (PDEs) due to their high computational intensity. The implementation of such solvers is highly interdisciplinary, which therefore requires an abstraction of hardware-specific parallelization techniques from developing numerical algorithms. We present an open-source run-time system (RTS) that distributes and parallelizes device-agnostic kernels, which define algorithms on unstructured grids. We describe how the RTS abstracts common parts of iterative solvers and further explain how to parallelize and distribute these components. We further show the efficiency of our approach for several microbenchmarks and an implementation of the discontinuous Galerkin method (DGM). The results show that we can almost completely hide all synchronization overhead and that the RTS only imposes a small computational cost.

关键词： Runtime system Finite Element Methods PGAS GASPI

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