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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

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hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis

Hardware synthesis from coarse-grained dataflow specificatio...

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Jung, H Ha, S Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul 151744 South Korea

ISBN: (纸本)1581139373

This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can be mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated.

关键词： HW/SW codesign system level design dataflow graph(DFG) VHDL autonomic hardware synthesis

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RTOS-centric hardware/software cosimulator for embedded system design

RTOS-centric hardware/software cosimulator for embedded syst...

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Honda, S Wakabayashi, T Tomiyama, H Takada, H Toyohashi Univ Technol Dept Informat & Comp Sci Toyohashi Aichi 4418580 Japan

ISBN: (纸本)1581139373

This paper presents an RTOS-centric hardware/software cosimulator which we have developed for embedded system design. One of the most remarkable features in our cosimulator is that it has a complete simulation model of an RTOS which is widely used in industry, so that application tasks including RTOS service calls are natively executed on a host computer. Our cosimulator also features cosimulation with functional simulation models of hardware written in C/C++ and cosimulation with HDL simulators. A case study with a JPEG decoder application demonstrates the effectiveness of our cosimulator.

关键词： RTOS cosimulation embedded systems

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Current flattening in software and hardware for security applications

Current flattening in software and hardware for security app...

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Muresan, R Gebotys, C Univ Guelph Guelph ON N1G 2W1 Canada

ISBN: (纸本)1581139373

This paper presents a new current flattening technique applicable in software and hardware. This technique is important in embedded cryptosystems since power analysis attacks (that make use of the current variation dependency on data and program) compromise the security of the system. The technique flattens the current internally by exploiting current consumption differences at the instruction level. Code transformations supporting current variation reductions due to program dependencies are presented. Also, a new real-time hardware architecture capable of reducing the current to data and program dependencies is proposed. Measured and simulated current waveforms of cryptographic software are presented in support of these techniques.

关键词： current flattening power analysis attacks hardware architecture

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A timing-accurate HW/SW Co-simulation of an ISS with systemC

A timing-accurate HW/SW Co-simulation of an ISS with SystemC

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Formaggio, L Fummi, F Pravadelli, G Univ Verona Dipartimento Informat I-37134 Verona Italy

ISBN: (纸本)1581139373

The paper presents a system level co-simulation methodology for modeling, validating, and analyzing the performance of embedded systems. The proposed solution relies on the integration between an instruction set simulator (ISS) and the systemC simulation kernel. In this way, the ISS is used to abstract the model of the real programmable device where the SW should run, while systemC is used to model HW components that interact with the SW. A correct validation of such an architecture is infeasible without taking care of timing information. Thus, the paper proposes an effective timing synchronization mechanism, which uses timing information of an ISS (or a board) to synchronize the systemC simulation.

关键词： system level modeling co-simulation

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system-on-chip validation using UML and CWL

System-on-chip validation using UML and CWL

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Zhu, Q Oishi, R Hasegawa, T Nakata, T Fujitsu Labs Ltd Nakahara Ku Kawasaki Kanagawa 2118588 Japan

ISBN: (纸本)1581139373

In this paper, a novel method for high-level specification and validation of SoC designs using UML is proposed. UML is introduced as a formal model of specification for SoC design. The consistency and completeness of the specification is validated based on the formal UML model. The implementation is validated by a systematic derivation of test scenarios and specification based coverage metrics from the UML model. The method has been applied to the design of a new media-processing chip for mobile devices. The application of the method shows that it is not only effective for finding logical errors in the implementation, but also eliminates errors due to inconsistency and incompleteness of the specification.

关键词： verification process UML validation and verification specification modeling

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Memory accesses management during high level synthesis

Memory accesses management during high level synthesis

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2nd international conference on hardware/software codesign and systems synthesis

作者： Corre, G Senn, E Bomel, P Julien, N Martin, E Univ S Brittany LESTER F-56321 Lorient France

ISBN: (纸本)1581139373

We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final Compatibility Graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time.

关键词： memory aware behavioral synthesis

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Future challenges in embedded systems 04

Future challenges in embedded systems

引用

Second IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2004

作者： Cuomo, Andrea Advanced System Technology ST Microelectronics

ISBN: (纸本)1581139373

Embedded systems will play a key role to drive the technological evolution in the next 20 years. Their evolution will further accelerate with the diffusion of the novel technologies that will deeply change our scenario, among which we can mention nanotechnologies, bioelectronics, and photonics. The central role of embedded systems in the economy will grow stronger and stronger: the starting point is the convergence between storage, security, video, audio, mobility and connectivity. systems are converging and ICs are more and more converging with systems: this poses a number of challenges for designers and technologists. A key issue is the definition of the right methodologies to translate system knowledge and competences into complex embedded systems, taking into account many system requirements and constraints. The key factor to win this challenge is to build the right culture. This means to be able to build the right environment to exploit existing design, architectural and technological solutions, and to favor the transfer of knowledge from one application field into another.

关键词： Embedded systems

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Cellular handset technology system requirements and integration trends

Cellular handset technology system requirements and integrat...

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： Mattisson, S Ericsson Mobile Platforms AB Strateg Prod Management Analog Syst Design SE-22183 Lund Sweden

ISBN: (纸本)1581139373

In ten years the cellular telephone has evolved from a tool for the professional to an indispensable consumer product with a very high market penetration. At the same time, the handset cost, weight, and standby time have been reduced by more than a factor of ten. These factors have been critical for the success story of the mobile phone. The technical aspects behind the rapid handset evolution are discussed. In particular, what advances in the radio architecture, for example the zero-IF GSM receiver, the baseband (CMOS) technology, and the radio system design areas have meant for the reduction of size, weight, cost, and power consumption is discussed. Future challenges, like SW-DSP-digital-RF partitioning, linear multi-mode modulation with high linearity requirements, digital leakage issues, and power consumption limitations in multimedia handsets are discussed with future generation handsets in mind.

关键词： Cellular telephone systems

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Efficient exploration of on-chip bus architectures and memory allocation

Efficient exploration of on-chip bus architectures and memor...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Kim, S Im, C Ha, SH Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul 151744 South Korea

ISBN: (纸本)1581139373

Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and mapping. In this paper we present an iterative two-step exploration methodology for bus-based on-chip communication architecture and memory allocation, assuming that memory traces from the processing elements are given from the mapping stage. The proposed method uses a static performance estimation technique to reduce the large design space drastically and quickly, and applies trace-driven simulation technique to the reduced set of design candidates for accurate performance estimation. Since local memory traffic as well as shared memory traffic are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. The viability and efficiency of the proposed methodology are validated by two real-life examples, 4-channel digital video recorder (DVR) and an equalizer for OFDM DVB-T receiver.

关键词： system-on-a-chip design space exploration communication architecture optimization memory allocation

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Facilitating reuse in hardware models with enhanced type inference

Facilitating reuse in hardware models with enhanced type inf...

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Second IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2004

作者： Vachharajani, Manish Vachharajani, Neil Malik, Sharad August, David I. Depts. of Comp. Sci. and Elec. Eng. Princeton University Princeton NJ 08544 United States

ISBN: (纸本)1581139373

High-level hardware modeling is an essential, yet time-consuming, part of system design. However, effective component-based reuse in hardware modeling languages can reduce model construction time and enable the exploration of more design alternatives, leading to better designs. While component overloading and parametric polymorphism are critical for effective component-base reuse, no existing modeling language supports both. The lack of these features creates overhead for designers that discourages reuse, negating any benefits of reuse. This paper presents a type system which supports both component overloading and parametric polymorphism. It proves that performing type inference for any such system is NP-complete and presents a heuristic that works efficiently in practice. The result is a type system and type inference algorithm that can encourage reuse, reduce design specification time, and lead to better designs.

关键词： Computer software reusability

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