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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

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A novel deadlock avoidance algorithm and its hardware implementation

A novel deadlock avoidance algorithm and its hardware implem...

引用

Second IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2004

作者： Lee, Jaehwan Mooney III, Vincent John Georgia Institute of Technology Atlanta GA United States

ISBN: (纸本)1581139373

This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provides a mechanism for very fast and automatic deadlock avoidance in MultiProcessor system-on-a-Chip (MP-SoC) with multiple (e.g., 10) processing elements and multiple (e.g., 40) resources. The DAU avoids deadlock by not allowing any grant or request that leads to a deadlock. In case of livelock, the DAU asks one of the processes involved in the livelock to release resource(s) so that the livelock can also be resolved. We simulated two realistic examples that can benefit from the DAU, and demonstrated that the DAU not only avoids deadlock in a few clock cycles but also achieves a 37% speed-up of application execution time over avoiding deadlock in software. Finally, the SoC area overhead due to the DAU is small, under 0.01% in our example.

关键词： Computer hardware

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Memory system design space exploration for low-power, real-time speech recognition

Memory system design space exploration for low-power, real-t...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Krishna, R Mahlke, S Austin, T Univ Michigan Adv Comp Architecture Lab Ann Arbor MI 48109 USA

ISBN: (纸本)1581139373

The recent proliferation of computing technology has generated new interest natural I/O interface technologies such as speech recognition. Unfortunately, the computational and memory demands of such applications currently prohibit their use on low-power portable devices in anything more than their simplest forms. Previous work has demonstrated that the thread level concurrency inherent in this application domain can be used to dramatically improve performance with minimal impact on overall system energy consumption, but that such benefits are severely constrained by memory system bandwidth. This work presents a design space exploration of potential memory system architectures. A range of low-power memory organizations are considered, from conventional caching to more advanced system-on-chip implementations. We find that, given architectures able to exploit concurrency in this domain, large L2 based cache hierarchies and high bandwidth memory systems employing data stream partitioning and on-chip embedded DRAM and ROM technologies can provide much of the performance of idealized memory systems without violating the power constraints of the low-power domain.

关键词： performance design

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Automatic synthesis of system on chip multiprocessor architectures for process networks

Automatic synthesis of system on chip multiprocessor archite...

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Second IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2004

作者： Dwivedi, Basant Kumar Kumar, Anshul Balakrishnan, M. Dept. of Comp. Sci. and Engineering Indian Institute of Technology Delhi New Delhi India

ISBN: (纸本)1581139373

In this paper, we present an approach for automatic synthesis of system on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is targeted towards design space exploration (DSE) and thus the speed of synthesis is of critical interest. The focus here is on the problem of resource allocation and binding with a view to optimize cost under performance constraints. Our approach exploits adjacency relation of processes and uses a dynamic programming based algorithm to synthesize the architecture including interconnection network. We have done a number of experiments on real as well as randomly generated process networks. The results have been compared with an optimal MILP formulation. They conclusively show that this approach is fast as well as effective and can be employed for DSE.

关键词： Computer architecture

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Fast co-simulation of transformative systems with OS support on SMP computer

Fast co-simulation of transformative systems with OS support...

引用

2nd international conference on hardware/software codesign and systems synthesis

作者： He, ZT Mok, A Univ Texas Dept Elect & Comp Engn Austin TX 78712 USA

ISBN: (纸本)1581139373

Transformative applications are a class of dataflow computation characterized by iterative behavior. The problem of partitioning a transformative application specification to a set of available hardware (HW) and software (SW) processing elements (PEs) and derivation of a job execution order (scheduling) on them has been quite well studied, but the problem of obtaining fast simulation of these applications poses different constraints. In this paper, we propose an efficient framework for a symmetric multi-processor (SMP) simulation host to achieve fast HW/SW co-simulation for transformative applications, given the partition solutions and the derived schedulers. The framework overcomes the limitations in existing Linux SMP kernel and requires only a reasonable amount of modifications to it. We also present a heuristic algorithm which effectively assigns simulation tasks to the processors on the simulation host, considering both average job simulation time on each processor and other simulation overhead. Our experiments show that the algorithm is able to find satisfactory suboptimal solutions with very little computation time. Based on the task assignment solution, the simulation time can be reduced by 25% to 50% from the obvious but naive approach.

关键词： HW/SW co-simulation transformative system task assignment SMP

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Power analysis of system-level on-chip communication architectures

Power analysis of system-level on-chip communication archite...

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2nd international conference on hardware/software codesign and systems synthesis

作者： Lahiri, K Raghunathan, A NEC Lab Amer Princeton NJ USA

ISBN: (纸本)1581139373

For complex system-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumption. Managing and optimizing this important component of SoC power requires a detailed understanding of the characteristics of its power consumption. Various power estimation and low-power design techniques have been proposed for the global interconnects that form part of SoC communication architectures (e.g., low-swing buses, bus encoding, etc). While effective, they only address a limited part of communication architecture power consumption. A state-of-the-art communication architecture, viewed in its entirety, is quite complex, comprising several components, such as bus interfaces, arbiters, bridges, decoders, and multiplexers, in addition to the global bus lines. Relatively little research has focused on analyzing and comparing the power consumed by different components of the communication architecture. In this work, we present a systematic evaluation and analysis of the power consumed by a state-of-the-art communication architecture (the AMBA on-chip bus), using a commercial design flow. We focus on developing a quantitative understanding of the relative contributions of different communication architecture components to its power consumption, and the factors on which they depend. We decompose the communication architecture power into power consumed by logic components (such as arbiters, decoders, bus bridges), global bus lines (that carry address, data, and control information), and bus interfaces. We also perform studies that analyze the impact of varying application traffic characteristics, and varying SoC complexity, on communication architecture power. Based on our analyses, we evaluate different techniques for reducing the power consumed by the on-chip communication architecture, and compare their effectiveness in achieving power savings at the system level. In addition to quanti

关键词： communication architectures system-on-chip low-power design power analysis network-on-chip

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Using C based logic synthesis to bridge the productivity gap

Using C based logic synthesis to bridge the productivity gap

引用

Asia and South Pacific Design Automation conference

作者： Sullivan, C Wilson, A Chappell, S Celoxica Ltd. United Kingdom

ISBN: (纸本)0780381750

Digital circuits from software designs and formal executable specifications can be automatically synthesized using hardware compilation or 'C based logic synthesis'. Designs can be verified using that same formal specification and coupled with the increasing deployment of higher-level C based languages and IP reuse in hardware design and system codesign, C based logic synthesis is enabling new methodologies and levels of designer productivity. In this paper we discuss the rationale for such a synthesis approach, the required semantics and compilation technology and offer a contrast with RTL synthesis. Design examples are used to provide case studies of practical experience.

关键词： Computer software

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A configurable logic architecture for dynamic hardware/software partitioning

A configurable logic architecture for dynamic hardware/softw...

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Design, Automation and Test in Europe conference and Exhibition (DATE 04)

作者： Lysecky, R Vahid, F Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)0769520855

In previous work, we showed the benefits and feasibility of having a processor dynamically partition its executing software such that critical software kernels are transparently partitioned to execute as a hardware coprocessor on configurable logic - an approach we call warp processing. The configurable logic place and route step is the most computationally intensive part of such hardware/software partitioning, normally running for many minutes or hours on powerful desktop processors. In contrast, dynamic partitioning requires place and route to execute in just seconds and on a lean embedded processor. We have therefore designed a configurable logic architecture specfically for dynamic hardware/software partitioning. Through experiments with popular benchmarks, we show that by specifically focusing on the goal of software kernel speedup when designing the FPGA architecture, rather than on the more general goal of ASIC prototyping, we can perform place and route for our architecture 50 times faster, using 10,000 times less data memory and 1,000 times less code memory, than popular commercial tools mapping to commercial configurable logic. Yet, we show that we obtain speedups (2x on average, and as much as 4x) and energy savings (33% on average, and up to 74%) when partitioning even just one loop, which are comparable to commercial tools and fabrics. Thus, our configurable logic architecture represents a good candidate for platforms that will support dynamic hardware/software partitioning, and enables ultra-fast desktop tools for hardware/software partitioning, and even for fast configurable logic design in general.

关键词： hardware/software partitioning FPGA fabric configurable logic synthesis place and route platforms system-on-a-chip dynamic optimization codesign self-improving chips just-in-time compilation warp processors reconfigurable computing

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On breakable cyclic definitions. 04

On breakable cyclic definitions.

引用

international conference on Computer Aided Design (ICCAD 2004)

作者： Jiang, JHR Mishchenko, A Brayton, RK Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA

ISBN: (纸本)0780387023

In the course of hardware system design or real-time process control, high-level specifications may contain simultaneous definitions of concurrent modules whose information flow forms cyclic dependencies without the separation of state-holding elements. The temporal behavior of these cyclic definitions may be meant to be combinational rather than sequential. Most prior approaches to analyzing cyclic combinational circuits were built upon the formulation of ternary-valued simulation at the circuit level. This paper shows the limitation of this formulation and investigates, at the functional level, the most general condition where cyclic definitions are semantically combinational. It turns out that the prior formulation is a special case of our treatment. Our result admits strictly more flexible high-level specifications. Furthermore, it allows a higher-level analysis of combinationality, and, thus, no costly synthesis of a high-level description into a circuit netlist before combinationality analysis can be performed. With our formulation, when the target is software implementations, combinational cycles need not be broken as long as the execution of the underlying system obeys a sequencing execution rule. For hardware implementations, combinational cycles are broken and replaced with acyclic equivalents at the functional level to avoid malfunctioning in the final physical realization.

关键词： hardware Circuit simulation Combinational circuits Analytical models Performance analysis Circuit synthesis Concurrent computing Real time systems Process control Resource management

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RTOS-centric hardware/software cosimulator for embedded system design 04

RTOS-centric hardware/software cosimulator for embedded syst...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： S. Honda T. Wakabayashi H. Tomiyama H. Takada Department of Information and Computer Science Toyohashi University of Technology Toyohashi Japan Graduate School of Information Science University of Nagoya Nagoya Japan

ISBN: (纸本)9781581139372

This work presents an RTOS-centric hardware/software cosimulator which we have developed for embedded system design. One of the most remarkable features in our cosimulator is that it has a complete simulation model of an RTOS which is widely used in industry, so that application tasks including RTOS service calls are natively executed on a host computer. Our cosimulator also features cosimulation with functional simulation models of hardware written in C/C++ and cosimulation with HDL simulators. A case study with a JPEG decoder application demonstrates the effectiveness of our cosimulator.

关键词： Embedded software Embedded system Computational modeling Application software hardware design languages Permission Computer science Information science Computer simulation Computer industry

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Current flattening in software and hardware for security applications 04

Current flattening in software and hardware for security app...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： R. Muresan C. Gebotys University of Guelph Guelph ONT Canada University of Waterloo Waterloo ONT Canada

ISBN: (纸本)9781581139372

This work presents a new current flattening technique applicable in software and hardware. This technique is important in embedded cryptosystems since power analysis attacks (that make use of the current variation dependency on data and program) compromise the security of the system. The technique flattens the current internally by exploiting current consumption differences at the instruction level. Code transformations supporting current variation reductions due to program dependencies are presented. Also, real-time hardware architecture capable of reducing the current to data and program dependencies is proposed. Measured and simulated current waveforms of cryptographic software are presented in support of these techniques.

关键词： hardware Application software Energy consumption Elliptic curve cryptography Public key cryptography Timing Data security Protocols Power system security Information analysis

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