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Design and programming of embedded multiprocessors: an interface-centric approach 04

Design and programming of embedded multiprocessors: an inter...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： P. van der Wolf E. de Kock T. Henriksson W. Kruijtzer G. Essink Philips Research Laboratories Eindhoven Netherlands

ISBN: (纸本)9781581139372

We present design technology for the structured design and programming of embedded multi-processor systems. It comprises a task-level interface that can be used both for developing parallel application models and as a platform interface for implementing applications on multi-processor architectures. Associated mapping technology supports refinement of application models towards implementation. By linking application development and implementation aspects, the technology integrates the specification and design phases in the MPSoC design process. Two design cases demonstrate the efficient implementation of the platform interface on different architectures. Industry-wide standardization of a task-level interface can facilitate reuse of function-specific hardware/software modules across companies.

关键词： hardware Application software Computer architecture Refining Process design Standardization Permission Joining processes Computer industry Parallel architectures

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A timing-accurate HW/SW cosimulation of an ISS with systemC 04

A timing-accurate HW/SW cosimulation of an ISS with SystemC

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： L. Formaggio F. Fummi G. Pravadelli Dipartirnento di lnformatica Università di Verona Verona Italy

ISBN: (纸本)9781581139372

The paper presents a system level co-simulation methodology for modeling, validating, and analyzing the performance of embedded systems. The proposed solution relies on the integration between an instruction set simulator (ISS) and the systemC simulation kernel. In this way, the ISS is used to abstract the model of the real programmable device where the SW should run, while systemC is used to model HW components that interact with the SW. A correct validation of such an architecture is infeasible without taking care of timing information. Thus, the paper proposes an effective timing synchronization mechanism, which uses timing information of an ISS (or a board) to synchronize the systemC simulation.

关键词： Timing Performance analysis Embedded system Engines hardware design languages Kernel system-level design Permission Discrete event simulation Computer languages

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Low energy security optimization in embedded cryptographic systems 04

Low energy security optimization in embedded cryptographic s...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： C.H. Gebotys Department of Elec and Comp Engineering University of Waterloo Waterloo ONT Canada

ISBN: (纸本)9781581139372

Future embedded and wireless devices are increasingly powerful supporting many applications including one of the most crucial; security. Although many wireless and embedded devices offer more resistance to bus probing attacks due to their compact size, susceptibility to power/electromagnetic attacks must be analyzed. This work presents optimized synthesis of new low energy masking countermeasures into cryptographic software. In particular a model for key masking with the objective of minimizing energy overhead is presented. Experimental results using real power measurements are shown to support up to 2.5 energy overhead savings and improved security compared to previous research. With the emergence of security applications in PDAs, cell phones, line card accelerators, etc, optimizing low energy countermeasures for resistance to power/ electromagnetic attacks is crucial for supporting future secure embedded devices.

关键词： Cryptography Power system security Communication system security Personal digital assistants Cellular phones Power measurement Electronic countermeasures Electromagnetic devices Smart cards Permission

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international conference on hardware/software codesign and systems synthesis (IEEE Cat. No.04TH8785)

International Conference on Hardware/Software Codesign and S...

引用

international conference on hardware/software codesign and system synthesis (CODES)

The following topics are dealt with: organic computing; design techniques for application specific processors; advances in software and hardware synthesis techniques for DSP applications; multiprocessor SoC design strategies and programming models; energy-aware compiling and scheduling; system-level design space exploration for hardware-software partitioning and platform instantiation; estimation and design techniques for energy-efficient memory systems; advances in hardware/software co-simulation techniques; NoC design and optimisation; software and hardware techniques for performance optimisation of embedded applications; techniques for security and reliability enhancement in embedded systems; and on-chip communication architecture analysis and optimisation.

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Efficient exploration of on-chip bus architectures and memory allocation 04

Efficient exploration of on-chip bus architectures and memor...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Sungchan Kim Chaeseok Im Soonhoi Ha School of Electrical Engineering and Computer Science Seoul National University Seoul South Korea

ISBN: (纸本)9781581139372

Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and mapping. We present an iterative two-step exploration methodology for bus-based on-chip communication architecture and memory allocation, assuming that memory traces from the processing elements are given from the mapping stage. The proposed method uses a static performance estimation technique to reduce the large design space drastically and quickly, and applies a trace-driven simulation technique to the reduced set of design candidates for accurate performance estimation. Since local memory traffic as well as shared memory traffic are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. The viability and efficiency of the proposed methodology are validated by two real-life examples, 4-channel digital video recorder (DVR) and an equalizer for OFDM DVB-T receiver.

关键词： Memory architecture Computer architecture system-on-a-chip Space exploration Traffic control Design methodology Permission Computer science Iterative methods Video sharing

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Cosynthesis of multiprocessor architectures with high availability

Cosynthesis of multiprocessor architectures with high availa...

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17th international conference on VLSI Design

作者： Chakraverty, S Netaji Subhas Inst Technol New Delhi 110045 India

ISBN: (纸本)0769520723

The co-synthesis of hardware-software systems for distributed and/or embedded applications has been studied extensively in the recent past, in combination with various qualitative objectives. However, the issues related to design exploration for gracefully degrading systems with the specific objective of achieving the desired levels of availability need to be addressed systematically. In this paper, we propose a cosynthesis mechanism for generating gracefully degrading multiprocessor architectures which fulfill the dual objectives of achieving real-time performance as well as ensuring high levels of system availability as defined by the user's availability expectations under different states of functionality. A rule-based model for incorporating the user's availability requirements and evaluating the system availability is coupled with a stochastic scheduling technique and a genetic algorithm (CA) to optimize the resource selections, task allocations and task schedules. Results show that it is possible to obtain a range of near-optimal solutions, offering tradeoffs between performance and availability benefits at different costs.

关键词： Computer hardware

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Memory system design space exploration for low-power, real-time speech recognition 04

Memory system design space exploration for low-power, real-t...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Rajeev Krishna S. Mahlke T. Austin Advanced Computer Architecture Laboratory University of Michigan Ann Arbor USA

ISBN: (纸本)9781581139372

The recent proliferation of computing technology has generated new interest natural I/O interface technologies such as speech recognition. Unfortunately, the computational and memory demands of such applications currently prohibit their use on low-power portable devices in anything more than their simplest forms. Previous work has demonstrated that the thread level concurrency inherent in this application domain can be used to dramatically improve performance with minimal impact on overall system energy consumption, but that such benefits are severely constrained by memory system bandwidth. This work presents a design space exploration of potential memory system architectures. A range of low-power memory organizations are considered, from conventional caching to more advanced system-on-chip implementations. We find that, given architectures able to exploit concurrency in this domain, large L2 based cache hierarchies and high bandwidth memory systems employing data stream partitioning and on-chip embedded DRAM and ROM technologies can provide much of the performance of idealized memory systems without violating the power constraints of the low-power domain.

关键词： Space exploration Real time systems Speech recognition Concurrent computing Bandwidth system-on-a-chip Space technology Portable computers Yarn Energy consumption

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Analyzing heap error behavior in embedded JVM environments 04

Analyzing heap error behavior in embedded JVM environments

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international conference on hardware/software codesign and system synthesis (CODES)

作者： G. Chen M. Kandemir N. Vijaykrishnan A. Sivasubramaniam M.J. Irwin Department of Computer Science and Engineering Pennsylvania State University University Park PA USA

ISBN: (纸本)9781581139372

Recent studies have shown that transient hardware errors caused by external factors such as alpha particles and cosmic ray strikes can be responsible for a large percentage of system down-time. Denser processing technologies, increasing clock speeds, and low supply voltages used in embedded systems can worsen this problem. In many embedded environments, one may not want to provision extensive error protection in hardware because of (i) form-factor or power consumption limitations, and/or (ii) to keep costs low. Also, the mismatch between the hardware protection granularity and the field access granularity can lead to false alarms and error cancellations. Consequently, software-based approaches to identify and possibly rectify these errors seem to be promising. Towards this goal, This work specifically looks to enhance the software's ability to detect heap memory errors in a Java-based embedded system. Using several embedded Java applications, This work first studies the tradeoffs between reliability, performance, and memory space overhead for two schemes that perform error checks at object and field granularities. We also study the impact of object characteristics (e.g., lifetime, re-use intervals, access frequency, etc.) on error propagation. Considering the pros and cons of these two schemes, we then investigate two hybrid strategies that attempt to strike a balance between memory space and performance overheads and reliability. Our experimental results clearly show that the granularity of error protection and its frequency can significantly impact static/dynamic overheads and error detection ability.

关键词： Error analysis hardware Embedded system Power system protection Java Frequency Alpha particles Clocks Low voltage Energy consumption

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Embedded systems education: How to teach the required skills?

Embedded systems education: How to teach the required skills...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： P. Marwedel D. Gajski E. De Kock H. De Man M. Sami I. Soderquist University of Dortmund Germany University of California Irvine USA Phillips Netherlands KU Leuven Belgium Saab Sweden

The goal of this panel is to contrast existing approaches to embedded system education with the needs in industry. Embedded system design is currently not yet well represented in academic programs. The general trend toward embedded systems requires a drastic change of that situation. This panel aims at starting a discussion on how current curricula should he revised in order to take the requirements of modem technologies into account.

关键词： Embedded system Educational programs hardware Application software Modems Communication system software Multimedia systems Streaming media software algorithms Algorithm design and analysis

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hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis 04

Hardware synthesis from coarse-grained dataflow specificatio...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Hyunuk Jung Soonhoi Ha School of Electrical Engineering and Computer Science Seoul National University Seoul South Korea

ISBN: (纸本)1581139373

This work concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can be mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated.

关键词： hardware system-level design Flow graphs Design methodology Logic Permission Computer science Data flow computing Finite impulse response filter Discrete cosine transforms

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