检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

995 篇 会议
40 篇 期刊文献

馆藏范围

1,035 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

542 篇 工学
- 512 篇 计算机科学与技术...
- 403 篇 软件工程
- 109 篇 电气工程
- 103 篇 电子科学与技术（可...
- 48 篇 信息与通信工程
- 40 篇 控制科学与工程
- 26 篇 机械工程
- 12 篇 建筑学
- 11 篇 动力工程及工程热...
- 7 篇 材料科学与工程（可...
- 6 篇 光学工程
- 6 篇 安全科学与工程
- 5 篇 土木工程
- 4 篇 生物工程
- 3 篇 生物医学工程（可授...
- 2 篇 力学（可授工学、理...
- 2 篇 仪器科学与技术
- 2 篇 化学工程与技术
113 篇 理学
- 68 篇 数学
- 46 篇 系统科学
- 11 篇 物理学
- 8 篇 统计学（可授理学、...
- 4 篇 生物学
67 篇 管理学
- 56 篇 管理科学与工程(可...
- 20 篇 工商管理
- 12 篇 图书情报与档案管...
10 篇 法学
- 6 篇 社会学
- 4 篇 法学
7 篇 艺术学
- 7 篇 设计学（可授艺术学...
5 篇 经济学
- 5 篇 应用经济学
1 篇 医学

主题

207 篇 hardware
113 篇 computer archite...
94 篇 embedded system
67 篇 application soft...
60 篇 embedded systems
60 篇 permission
55 篇 system-on-a-chip
51 篇 computational mo...
48 篇 field programmab...
47 篇 algorithm design...
47 篇 software
41 篇 energy consumpti...
40 篇 costs
37 篇 system-on-chip
34 篇 real time system...
34 篇 space exploratio...
34 篇 embedded softwar...
32 篇 timing
32 篇 high level synth...
31 篇 system-level des...

机构

8 篇 center for embed...
8 篇 department of el...
7 篇 univ calif river...
7 篇 department of co...
6 篇 school of comput...
6 篇 arizona state un...
6 篇 center for embed...
6 篇 institute for in...
5 篇 princeton univ d...
5 篇 school of inform...
5 篇 philips research...
5 篇 university of er...
5 篇 nec laboratories...
4 篇 natl taiwan univ...
4 篇 department of co...
4 篇 politecn torino ...
4 篇 carnegie mellon ...
4 篇 tu braunschweig
4 篇 university of ca...
4 篇 university of do...

作者

9 篇 sri parameswaran
9 篇 ogras umit y.
9 篇 nikil dutt
8 篇 leupers rainer
7 篇 rolf ernst
7 篇 teich juergen
7 篇 robert p. dick
7 篇 parameswaran sri
6 篇 jiang wei
6 篇 dick robert p.
6 篇 dutt nikil
6 篇 mitra tulika
6 篇 rainer leupers
6 篇 andreas gerstlau...
6 篇 jha niraj k.
5 篇 pasricha sudeep
5 篇 gerd ascheid
5 篇 greg stitt
5 篇 jinyu zhan
5 篇 ernst rolf

语言

1,029 篇 英文
6 篇 其他

检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

共 1035 条记录，以下是821-830 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Exploiting polymorphism in HW design: a case study in the ATM domain 04

Exploiting polymorphism in HW design: a case study in the AT...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： L. Pomante CEFRIEL Milano Italy

ISBN: (纸本)9781581139372

The need of raising the level of abstraction and improving reuse in HW design suggests the adoption of an object-oriented (OO) design methodology based on systemC-Plus (i.e. an enhanced systemC). Such a methodology, developed during the ODETTE IST project, allows the exploitation of the key features of the OO paradigm (i.e. information hiding, inheritance, and polymorphism) at the behavioral level of description while guaranteeing synthesizability. In this context, the goal of This work is to highlight advantages and drawbacks derived from the exploitation of polymorphism in the design of an ATM component: the UTOPIA cells handler.

关键词： Computer aided software engineering Object oriented modeling Design methodology hardware High level synthesis Permission Process design Integrated circuit synthesis Algorithm design and analysis Integrated circuit technology

来源：评论

学校读者我要写书评

暂无评论

Fast exploration of bus-based on-chip communication architectures 04

Fast exploration of bus-based on-chip communication architec...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： S. Pasricha N. Dutt M. Ben-Romdhane Center for Embedded Computer Systems University of California Irvine CA USA Center for Embedded Computer Systems University of California Irvine CA Conexant Systems Inc. Newport Beach CA USA

ISBN: (纸本)9781581139372

As a result of improvements in process technology, more and more components are being integrated into a single system-on-chip (SoC) design. Communication between these components is increasingly dominating critical system paths and frequently becomes the source of performance bottlenecks. It therefore becomes extremely important for designers to explore the communication space early in the design flow. Traditionally, pin-accurate bus cycle accurate (PA-BCA) models were used for exploring the communication space. To speed up simulation, transaction based bus cycle accurate (T-BCA) models have been proposed, which borrow concepts found in the transaction level modeling (TLM) domain. The cycle count accurate at transaction boundaries (CCATB) modeling abstraction was introduced for fast communication space exploration. In This work, we describe the mechanisms that produce the speedup in CCATB models and demonstrate the effectiveness of the CCATB exploration approach with the aid of a case study involving an AMBA 2.0 based SoC subsystem used in the multimedia application domain. We also analyze how the achieved simulation speedup scales with design complexity and show that SoC designs modeled at the CCATB level simulate 120% faster than PA-BCA and 67% faster than T-BCA models on average.

关键词： Space exploration system-on-a-chip Computer architecture Space technology Analytical models Permission Embedded computing Multiprocessing systems Application specific integrated circuits High level languages

来源：评论

学校读者我要写书评

暂无评论

Secure and safety-critical vs. insecure, non safety-critical embedded systems: do they require completely different design approaches? 04

Secure and safety-critical vs. insecure, non safety-critical...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： P. Marwedel C. Gebotys University of Dortmund and ICD University of Waterloo

ISBN: (纸本)9781581139372

As we move forward into the era of ubiquitous pervasive computing, the design of secure safety-critical systems will become increasingly complex. For example, future automobiles will become the ultimate mobile wireless device containing a distributed network with multiple vendor software and hardware. However the carýs embedded software which is expected to increase in size by 100 fold, will create a significant impact on the overall system safety. Furthermore wireless communications may create the possibility of terrorists or attackers gaining control of the automobile, hence security is also an important issue. How will designers cope with this complexity while at the same time ensure safety and security? Will new design approaches be required? Or can current design methodologies be used with new metrics, safety and security? This panel will bring together experts from the safety-critical industry, security industry, and experts from the insecure non-safety critical industry.

关键词： Embedded system Automobiles software safety Communication system security hardware Embedded software Hazards Smart cards Immune system software systems

来源：评论

学校读者我要写书评

暂无评论

Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management 04

Parallel programming models for a multi-processor SoC platfo...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： P.G. Paulin C. Pilkington M. Langevin E. Bensoudane G. Nicolescu Central Research and Development STMicroelectronics Inc. Ottawa Canada Ecole Polytechnique de Montreal Montreal Canada

ISBN: (纸本)9781581139372

We describe the MultiFlex multi-processor SoC programming environment, with the focus on two programming models: a distributed system object component (DSOC) message passing model, and a symmetrical multi-processing (SMP) model using shared memory. The MultiFlex tools map these models onto the StepNP multi-processor SoC platform, while making use of hardware accelerators for message passing and task scheduling. We present the results of mapping an Internet traffic management application, running at 2.5 Gb/s.

关键词： Parallel programming Traffic control Message passing Delay Network-on-a-chip Context modeling hardware Research and development Programming environments Job shop scheduling

来源：评论

学校读者我要写书评

暂无评论

Power analysis of system-level on-chip communication architectures 04

Power analysis of system-level on-chip communication archite...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： K. Lahiri A. Raghunathan NEC Laboratories of America Inc. Princeton NJ USA

ISBN: (纸本)9781581139372

For complex system-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumption. Managing and optimizing this important component of SoC power requires a detailed understanding of the characteristics of its power consumption. Various power estimation and low-power design techniques have been proposed for the global interconnects that form part of SoC communication architectures (e.g., low-swing buses, bus encoding, etc). While effective, they only address a limited part of communication architecture power consumption. A state-of-the-art communication architecture, viewed in its entirety, is quite complex, comprising several components, such as bus interfaces, arbiters, bridges, decoders, and multiplexers, in addition to the global bus lines. Relatively little research has focused on analyzing and comparing the power consumed by different components of the communication architecture. In this work, we present a systematic evaluation and analysis of the power consumed by a state-of-the-art communication architecture (the AMBA on-chip bus), using a commercial design flow. We focus on developing a quantitative understanding of the relative contributions of different communication architecture components to its power consumption, and the factors on which they depend. We decompose the communication architecture power into power consumed by logic components (such as arbiters, decoders, bus bridges), global bus lines (that carry address, data, and control information), and bus interfaces. We also perform studies that analyze the impact of varying application traffic characteristics, and varying SoC complexity, on communication architecture power. Based on our analyses, we evaluate different techniques for reducing the power consumed by the on-chip communication architecture, and compare their effectiveness in achieving power savings at the system level. In addition to quanti

关键词： system-on-a-chip Energy consumption Bridges Decoding Energy management Power system management Power system interconnection Encoding Multiplexing Logic

来源：评论

学校读者我要写书评

暂无评论

Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs 04

Tuning SoC platforms for multimedia processing: identifying ...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： A. Maxiaguine Yongxin Zhu Samarjit Chakraborty Weng-Fai Wong Computer Engineering and Networks Laboratory ETH Zürich Switzerland Department of Computer Science National University of Singapore Singapore

ISBN: (纸本)9781581139372

We present an analytical framework to identify the tradeoffs and performance impacts associated with different SoC platform configurations in the specific context of implementing multimedia applications. "Configurations" in this case might include sizes of different on-chip buffers and scheduling mechanisms (or associated parameters) implemented on the different processing elements of the platform. Identifying such tradeoffs is difficult because of the bursty nature of on-chip traffic arising out of multimedia processing and the high variability in their execution requirements, which result in a highly irregular design space. We show that this irregularity in the design space can be precisely captured using an abstraction called variability characterization curves.

关键词： Processor scheduling Time division multiple access system-on-a-chip Multimedia systems Costs Permission hardware Computer networks Laboratories Computer science

来源：评论

学校读者我要写书评

暂无评论

Automatic synthesis of system on chip multiprocessor architectures for process networks 04

Automatic synthesis of system on chip multiprocessor archite...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： B.K. Dwivedi A. Kumar M. Balakrishnan Dept. of Computer Science and Engineering Indian Institute of Technology Delhi New Delhi India

ISBN: (纸本)9781581139372

We present an approach for automatic synthesis of system on chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is targeted towards design space exploration (DSE) and thus the speed of synthesis is of critical interest. The focus here is on the problem of resource allocation and binding with a view to optimize cost under performance constraints. Our approach exploits adjacency relation of processes and uses a dynamic programming based algorithm to synthesize the architecture including interconnection network. We have done a number of experiments on real as well as randomly generated process networks. The results have been compared with an optimal MILP formulation. They conclusively show that this approach is fast as well as effective and can be employed for DSE.

关键词： Network synthesis system-on-a-chip Space exploration Resource management Constraint optimization Cost function Dynamic programming Heuristic algorithms Multiprocessor interconnection networks Random number generation

来源：评论

学校读者我要写书评

暂无评论

A novel deadlock avoidance algorithm and its hardware implementation

A novel deadlock avoidance algorithm and its hardware implem...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Jaehwan Lee V.J. Mooney Georgia Institute of Technology Atlanta GA USA

This work proposes a deadlock avoidance algorithm (DAA) and its hardware implementation, the deadlock avoidance unit (DAU), as an intellectual property (IP) core that provides a mechanism for very fast and automatic deadlock avoidance in multiprocessor system-on-a-chip (MP-SoC) with multiple (e.g., 10) processing elements and multiple (e.g., 40) resources. The DAU avoids deadlock by not allowing any grant or request that leads to a deadlock. In case of livelock, the DAU asks one of the processes involved in the livelock to release resource(s) so that the livelock can also be resolved. We simulated two realistic examples that can benefit from the DAU, and demonstrated that the DAU not only avoids deadlock in a few clock cycles but also achieves a 37% speed-up of application execution time over avoiding deadlock in software. Finally, the SoC area overhead due to the DAU is small, under 0.01% in our example.

关键词： system recovery hardware system-on-a-chip Resource management Application software Algorithm design and analysis Permission Intellectual property Multiprocessing systems Clocks

来源：评论

学校读者我要写书评

暂无评论

Analytical models for leakage power estimation of memory array structures 04

Analytical models for leakage power estimation of memory arr...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： M. Mamidipaka K. Khouri N. Dutt M. Abadir Center for Embedded Computer Systems University of California Irvine CA USA Global Strategy and Future Tools & Meth. Freescale/Motorola Inc. Austin TX USA

ISBN: (纸本)9781581139372

There is a growing need for accurate power models at the system level. Memory structures such as caches, branch target buffers (BTBs), and register files occupy significant area in contemporary SoC designs and are the main contributors to system leakage power dissipation. Existing models for leakage power estimation in array structures typically use coefficients derived from elaborate SPICE simulations. However, these methodologies are not applicable to array designs in a newer technology, that require power estimates early in the design cycle. In this paper, we propose analytical models for array structures that are based only on high level design parameters. Assuming typical circuit implementation styles, we identify the transistors that contribute to the leakage power in each array sub-circuit and develop models as a function of the operation (read/write/idle) on the array and organizational parameters of the array. The developed models are validated by comparing their estimates against the leakage power measured using SPICE simulations on industrial array designs belonging to the e500 processor core. The comparison shows that the models are accurate with an error margin of less than 21.5% and thus can be used in high-level power-performance exploration. Interestingly, in array designs with dual threshold voltage technology, we observed that contrary to the general expectation, the array memory core contributes to just 9% and the address decoder contributes to as much as 62% of the total leakage power.

关键词： Analytical models Power dissipation Power system modeling SPICE Embedded computing Registers Circuit simulation Power measurement Threshold voltage Decoding

来源：评论

学校读者我要写书评

暂无评论

Organic computing - on the feasibility of controlled emergence 04

Organic computing - on the feasibility of controlled emergen...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： C. Muller-Schloer Institute of Systems Engineering-System and Computer Architecture (SRA) Universität Hannover Hanover Germany

ISBN: (纸本)9781581139372

This work gives an introduction to the research area of organic computing and shows chances, opportunities and problems currently tackled by researchers. First the visions that lead to this research area are discussed briefly. It is shown that the notion of emergence, a central phenomenon in organic computing, is a typical bottom-up effect with the interesting property of generating order from randomness. The classical design, however, is a top-down process. This apparent contradiction can be overcome by introducing so-called observer/controller architectures leading to the possibility to controlled emergence. The paper concludes with a description of current research problems in organic computing.

关键词： Telecommunication computing Computer architecture Artificial intelligence Application software Permission Web and internet services systems engineering and theory Mobile computing Intelligent agent Multiagent systems

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共104页 << < 79 80 81 82 83 84 85 86 87 88 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：