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Memory accesses management during high level synthesis 04

Memory accesses management during high level synthesis

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international conference on hardware/software codesign and system synthesis (CODES)

作者： G. Corre E. Senn P. Bornel N. Julien E. Martin LESTER University of South Brittany LORIENT cedex France LESTER South Brittany Univ. Lorient France

ISBN: (纸本)9781581139372

We introduce an approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We formalize the memory mapping as a set of constraints for the synthesis, and defined a memory constraint graph and an accessibility criterion to be used in the scheduling step. We present a strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final compatibility graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time.

关键词： Memory management High level synthesis Signal synthesis Algorithm design and analysis Scheduling algorithm Flow graphs Costs Registers Memory architecture Aging

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Optimizing the memory bandwidth with loop fusion

Optimizing the memory bandwidth with loop fusion

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international conference on hardware/software codesign and system synthesis (CODES)

作者： P. Marchal F. Catthoor J.I. Gomez KU Leuven Heverlee Belgium DACYA/UCM Madrid Spain

The memory bandwidth largely determines the performance and energy cost of embedded systems. At the compiler level, several techniques improve the memory bandwidth at the scope of a basic block, but often fail to exploit all. We propose a technique to optimize the memory bandwidth across the boundaries of a basic block. Our technique incrementally fuses loops to better use the available bandwidth. The resulting performance depends on how the data is assigned to the memories of the memory layer. At the same time, the assignment also strongly influences the energy cost. Therefore, we combine in our approach the fusion and assignment decisions. Designers can use our output to trade-off the energy cost with the system's performance.

关键词： Bandwidth Costs Fuses Processor scheduling Permission Embedded system Algorithm design and analysis Delay Optimizing compilers Data structures

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Facilitating reuse in hardware models with enhanced type inference 04

Facilitating reuse in hardware models with enhanced type inf...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： M. Vachharajani N. Vachharajani S. Malik D.I. August Departments of Computer Science and Electrical Engineering Princeton University Princeton NJ USA

ISBN: (纸本)9781581139372

High-level hardware modeling is an essential, yet time-consuming, part of system design. However, effective component-based reuse in hardware modeling languages can reduce model construction time and enable the exploration of more design alternatives, leading to better designs. While component overloading and parametric polymorphism are critical for effective component-base reuse, no existing modeling language supports both. The lack of these features creates overhead for designers that discourages reuse, negating any benefits of reuse. This work presents a type system which supports both component overloading and parametric polymorphism. It proves that performing type inference for any such system is NP-complete and presents a heuristic that works efficiently in practice. The result is a type system and type inference algorithm that can encourage reuse, reduce design specification time, and lead to better designs.

关键词： hardware Algorithm design and analysis Concrete Inference algorithms Computer languages Space exploration Computer science Lead time reduction Buildings Permission

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system-on-chip validation using UML and CWL 04

System-on-chip validation using UML and CWL

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Q. Zhu R. Oishi T. Hasenawa T. Nakata Fujitsu Laboratories LTD Nakahara-ku Kawasaki Japan

ISBN: (纸本)9781581139372

A novel method for high-level specification and validation of SoC designs using UML is proposed. UML is introduced as a formal model of specification for SoC design. The consistency and completeness of the specification is validated based on the formal UML model. The implementation is validated by a systematic derivation of test scenarios and specification based coverage metrics from the UML model. The method has been applied to the design of a new media-processing chip for mobile devices. The application of the method shows that it is not only effective for finding logical errors in the implementation, but also eliminates errors due to inconsistency and incompleteness of the specification.

关键词： Unified modeling language Object oriented modeling Protocols Process design Computer architecture Timing Programming Specification languages Intellectual property Testing

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Using invariants to optimize formal specifications before code synthesis

Using invariants to optimize formal specifications before co...

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Proceedings - 2nd acm and IEEE international conference on Formal Methods and Models for Co-Design, MEMOCODE'04

作者： Jeffords, Ralph D. Leonard, Elizabeth I. Washington DC 20375 United States

ISBN: (纸本)0780385098

Formal specifications of required system behavior can be analyzed, verified, and validated, giving high confidence that the specification captures the desired behavior. Transferring this confidence to the system implementation depends on a formal link between requirements and implementation. The automatic generation of provably correct code provides just such a link. While optimization is usually performed on code to achieve efficiency, we propose to optimize the formal specification before generating code, thus providing optimization independent of the particular code generation method. This paper investigates the use of invariants in optimizing code generated from formal specifications in the software Cost Reduction (SCR) tabular notation. We show that invariants (1) provide the basis for simplifying expressions that otherwise cannot be improved using traditional compiler optimization techniques, and (2) allow detection and elimination of parts of the specification that would lead to unreachable code. © 2004 IEEE.

关键词： Computer hardware description languages

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Power-performance trade-offs for reconfigurable computing 04

Power-performance trade-offs for reconfigurable computing

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international conference on hardware/software codesign and system synthesis (CODES)

作者： J. Noguera R.M. Badia Research & Development Department Hewlett Packard Company USA Computer Architecture Department (DAC) Technical University of Catalonia Spain

ISBN: (纸本)9781581139372

We explore the system-level power-performance trade-offs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. We show that an efficient hardware-software partitioning algorithm is required when targeting low-power. However, if the application objective is performance, then we propose the use of dynamically reconfigurable architectures. This work presents a configuration-aware data size partitioning approach. We propose a design methodology that adapts the architecture and used algorithms to the application requirements. The methodology has been proven to work on a real research platform based on Xilinx devices. Finally, we have applied our methodology and algorithms to the case study of image sharpening, which is required nowadays in digital cameras and mobile phones.

关键词： Reconfigurable architectures Processor scheduling Partitioning algorithms Computer architecture Dynamic scheduling system-on-a-chip Programmable logic arrays Programmable logic devices Design methodology Reconfigurable logic

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Energy-efficient flash-memory storage systems with an interrupt-emulation mechanism 04

Energy-efficient flash-memory storage systems with an interr...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Chin-Hsien Wu Tei-Wei Kuo Chia-Lin Yang Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan

ISBN: (纸本)1581139373

One of the emerging critical issues for flash-memory storage systems, especially on the implementations of many embedded systems, is on its programmed I/O nature for data transfers. Programmed-I/O-based data transfers might not only result in the wasting of valuable CPU cycles of microprocessors but also unnecessarily consume much more energy from batteries. This work presents an interrupt-emulation mechanism for flash-memory storage systems with an energy-efficient management strategy. We propose to revise the waiting function in the memory-technology-device (MTD) layer to relieve the microprocessor from busy waiting and to reduce the energy consumption of the system. We show that energy consumption could be significantly reduced with good saving on CPU cycles and minor delay on the average response time in the experiments.

关键词： Energy efficiency Energy storage Flash memory Embedded system Microprocessors Energy consumption Batteries Delay Emulation Permission

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Cellular handset technology system requirements and integration trends 04

Cellular handset technology system requirements and integrat...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： S. Mattisson Strategic Product Management Analog System Design Lund Sweden

ISBN: (纸本)9781581139372

Summary form only given. Cellular handset technology system requirements and integration trends In ten years the cellular telephone has evolved from a tool for the professional to an indispensable consumer product with a very high market penetration. At the same time, the handset cost, weight, and standby time have been reduced by more than a factor often. These factors have been critical for the success story of the mobile phone. The technical aspects behind the rapid handset evolution are discussed. In particular, what advances in: the radio architecture, for example the zero-IF GSM receiver; the baseband (CMOS) technology; and the radio system design areas have meant for the reduction of size, weight, cost, and power consumption is discussed. Future challenges, like SW-DSP-digital-RF partitioning, linear multi-mode modulation with high linearity requirements, digital leakage issues, and power consumption limitations in multimedia handsets are discussed with future generation handsets in mind.

关键词： Telephone sets Costs CMOS technology Energy consumption Telephony Consumer products Mobile handsets GSM Receivers Baseband

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Dual-pipeline heterogeneous ASIP design 04

Dual-pipeline heterogeneous ASIP design

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： S. Radhakrishnan Hui Guo S. Parameswaran School of Computer Science & Engineering University of New South Wales Sydney Australia

ISBN: (纸本)9781581139372

We demonstrate the feasibility of a dual pipeline application specific instruction set processor. We take a C program and create a target instruction set by compiling to a basic instruction set from which some instructions are merged, while others discarded. Based on the target instruction set, parallelism of the application program is analyzed and two unique instruction sets are generated for a heterogeneous dual-pipeline processor. The dual pipe processor is created by making two unique ASIPs (VHDL descriptions) utilizing the ASIP-Meister Tool Suite, and fusing the two VHDL descriptions to construct a dual pipeline processor. Our results show that in comparison to the single pipeline application specific instruction set processor, the performance improves by 27.6% and switching activity reduces by 6.1% for a number of benchmarks. These improvements come at the cost of increased area which for benchmarks considered is 16.7% on average.

关键词： Application specific processors Pipelines Embedded system Space exploration Costs Application software VLIW Instruction sets Telephony Personal digital assistants

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CPU scheduling for statistically-assured real-time performance and improved energy efficiency 04

CPU scheduling for statistically-assured real-time performan...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Haisang Wu B. Ravindran E.D. Jensen Peng Li ECE Dept. Virginia Tech Blacksburg VA USA The MITRE Corporation Bedford MA USA

ISBN: (纸本)9781581139372

We present a CPU scheduling algorithm, called energy-efficient utility accrual algorithm (or EUA), for battery-powered, embedded real-time systems. We consider an embedded software application model where repeatedly occurring application activities are subject to deadline constraints specified using step time/utility functions. For battery-powered embedded systems, system-level energy consumption is also a primary concern. We consider CPU scheduling that (1) provides assurances on individual and collective application timeliness behaviors and (2) maximizes system-level timeliness and energy efficiency. Since the scheduling problem is intractable, EUA heuristically computes CPU schedules with a polynomial-time cost. Several properties of EUA are analytically established, including timeliness optimality during under-load situations and statistical assurances on timeliness behavior. Further, our simulation results confirm EUA's superior performance.

关键词： Energy efficiency Application software Processor scheduling Scheduling algorithm Real time systems Embedded software Embedded system Energy consumption Polynomials Costs

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