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Efficient search space exploration for HW-SW partitioning 04

Efficient search space exploration for HW-SW partitioning

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： S. Banerjee N. Dutt Center for Embedded Computer Systems University of California Irvine CA USA

ISBN: (纸本)9781581139372

hardware/software (HW-SW) partitioning is a key problem in the codesign of embedded systems, studied extensively in the past. One major open challenge for traditional partitioning approaches - as we move to more complex and heterogeneous SoCs - is the lack of efficient exploration of the large space of possible HW/SW configurations, coupled with the inability to efficiently scale up with larger problem sizes. We make two contributions for HW-SW partitioning of applications represented as procedural call-graphs: 1) we prove that during partitioning, the execution time metric for moving a vertex needs to be updated only for the immediate neighbours of the vertex, rather than for all ancestors along paths to the root vertex; consequently, we observe faster run-times for move-based partitioning algorithms such as simulated annealing (SA), allowing call graphs with thousands of vertices to be processed in less than a second, and 2) we devise a new cost function for SA that allows frequent discovery of better partitioning solutions by searching spaces overlooked by traditional SA cost functions. We present experimental results on a very large design space, where several thousand configurations are explored in minutes as compared to several hours or days using a traditional SA formulation. Furthermore, our approach is frequently able to locate better design points with over 10 % improvement in application execution time compared to the solutions generated by a Kernighan-Lin partitioning algorithm starting with an all-SW partitioning.

关键词： Space exploration Partitioning algorithms Cost function hardware Embedded software Embedded system Runtime Simulated annealing Extraterrestrial measurements Algorithm design and analysis

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Detecting overflow detection 04

Detecting overflow detection

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： V. Kotlyar M. Moudgill Sandbridge Technologies Inc. White Plains NY USA

ISBN: (纸本)9781581139372

Fixed-point saturating arithmetic is widely used in media and digital signal processing applications. A number of processor architectures provide instructions that implement saturating operations. However, standard high-level languages, such as ANSI C, provide no direct support for saturating arithmetic. Applications written in standard languages have to implement saturating operations in terms of basic two's complement operations. In order to provide fast execution of such programs it is important to have an optimizing compiler automatically detect and convert appropriate code fragments to hardware instructions. We present a set of techniques for automatic recognition of saturating arithmetic operations. We show that in most cases the recognition problem is simply one of Boolean circuit equivalence. Given the expense of solving circuit equivalence, we develop a set of practical approximations based on abstract interpretation. Experiments show that our techniques, while reliably recognizing saturating arithmetic, have small compile-time overhead. We also demonstrate that our approach is not limited to saturating arithmetic, but is directly applicable to recognizing other idioms, such as add-with-carry and absolute value.

关键词： software libraries Digital arithmetic Fixed-point arithmetic Digital signal processing ANSI standards Circuits Computer languages Permission High level languages Optimizing compilers

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Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures 04

Efficient mapping of hierarchical trees on coarse-grain reco...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： F. Rivera M. Sanchez-Elez M. Fernandez R. Hermida N. Bagherzadeh Departmento de Arquitectura de Computadores y Automática Universidad Computadores Madrid Spain Depto. de Arquitectura de Computadores y Automática Universidad Complutense Madrid SPAIN Dept. of Electrical and Computing Engineering University of California Irvine CA USA

ISBN: (纸本)9781581139372

Reconfigurable architectures have become increasingly important in years. We present an approach to the problem of executing 3D graphics interactive applications onto these architectures. The hierarchical trees are usually implemented to reduce the data processed, thereby diminishing the execution time. We have developed a mapping scheme that parallelizes the tree execution onto a SIMD reconfigurable architecture. This mapping scheme considerably reduces the time penalty caused by the possibility of executing different tree nodes in SIMD fashion. We have developed a technique that achieves an efficient hierarchical tree execution taking decisions at execution time. It also promotes the possibility of data coherence in order to reduce the execution time. The experimental results show high performance and efficient resource utilization on tested applications.

关键词： Vegetation mapping Reconfigurable architectures Computer architecture Tree graphs Application software Streaming media Digital signal processing Permission Graphics Resource management

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Fast cosimulation of transformative systems with OS support on SMP computer

Fast cosimulation of transformative systems with OS support ...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Zhengting He A. Mok Department of Electrical & Computer Engineering University of Texas Austin Austin TX USA Department of Computer Science University of Texas Austin Austin TX USA

Transformative applications are a class of dataflow computation characterized by iterative behavior. The problem of partitioning a transformative application specification to a set of available hardware (HW) and software (SW) processing elements (PEs) and derivation of a job execution order (scheduling) on them has been quite well studied, but the problem of obtaining fast simulation of these applications poses different constraints. In this paper, we propose an efficient framework for a symmetric multi-processor (SMP) simulation host to achieve fast HW/SW co-simulation for transformative applications, given the partition solutions and the derived schedulers. The framework overcomes the limitations in existing Linux SMP kernel and requires only a reasonable amount of modifications to it. We also present a heuristic algorithm which effectively assigns simulation tasks to the processors on the simulation host, considering both average job simulation time on each processor and other simulation overhead. Our experiments show that the algorithm is able to find satisfactory suboptimal solutions with very little computation time. Based on the task assignment solution, the simulation time can be reduced by 25% to 50% from the obvious but naive approach.

关键词： Operating systems Computational modeling Application software Permission Codecs Helium hardware Processor scheduling Linux Kernel

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Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures 04

Fast cycle-accurate simulation and instruction set generatio...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： S.J. Weber M.W. Moskewicz M. Gries C. Sauer K. Keutzer University of California Electronics Research Lab Berkeley USA Infineon Technologies Corporate Research Munich Germany

ISBN: (纸本)9781581139372

State-of-the-art architecture description languages have been successfully used to model application-specific programmable architectures limited to particular control schemes. We introduce a language and methodology that provide a framework for constructing and simulating a wider range of architectures. The framework exploits the fact that designers are often only concerned with data paths, not the instruction set and control. In the framework, each processing element is described in a structural language that only requires the specification of the data path and constraints on how it can be used. From such a description, the supported operations of the processing clement are automatically extracted and a controller is generated. Various architectures are then realized by composing the processing elements. Furthermore, hardware descriptions and bit-true cycle-accurate simulators are automatically generated. Results show that our simulators are up to an order of magnitude faster than other reported simulators of this type and two orders of magnitude faster than equivalent Verilog simulations.

关键词： Computational modeling Data mining Automatic generation control Automatic control Architecture description languages hardware design languages Computer simulation Permission Computer architecture Computer languages

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Benchmark-based design strategies for single chip heterogeneous multiprocessors 04

Benchmark-based design strategies for single chip heterogene...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： J.M. Paul D.E. Thomas A. Bobrek Electrical and Computer Engineering Department Carnegie Mellon University Pittsburgh PA USA

ISBN: (纸本)9781581139372

Single chip heterogeneous multiprocessors are arising to meet the computational demands of portable and handheld devices. These computing systems are not fully custom designs traditionally targeted by the design automation (DA) community, general purpose designs traditionally targeted by the computer architecture (CA) community, nor pure embedded designs traditionally targeted by the real-time (RT) community. An entirely new design philosophy will be needed for this hybrid class of computing. The programming of the device will be drawn from a narrower set of applications with execution that persists in the system over a longer period of time than for general purpose programming. But the devices will still be programmable, not only at the level of the individual processing element, but across multiple processing elements and even the entire chip. The design of other programmable single chip computers has enjoyed an era where the design trade-offs could be captured in simulators such as SimpleScalar and performance could be evaluated to the SPEC benchmarks. Motivated by this, we describe new benchmark-based design strategies for single chip heterogeneous multiprocessors. We include an example and results.

关键词： Application software Computer architecture Computational modeling Design automation Design optimization Bandwidth Application specific integrated circuits Embedded system Embedded computing Benchmark testing

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Dynamic overlay of scratchpad memory for energy minimization 04

Dynamic overlay of scratchpad memory for energy minimization

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international conference on hardware/software codesign and system synthesis (CODES)

作者： M. Verma L. Wehmeyer P. Marweclel Department of Computer Science XII University of Dortmund Dortmund Germany Technische Universitat Dortmund Dortmund Nordrhein-Westfalen DE Dept. of Comput. Sci. Dortmund Univ. Germany

ISBN: (纸本)9781581139372

The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing the energy consumption of the memory subsystem. Consequently, novel memories as well as novel algorithms for their efficient utilization are being designed. Scratchpads are known to perform better than caches in terms of power, performance, area and predictability. However, unlike caches they depend upon software allocation techniques for their utilization. We present an allocation technique which analyzes the application and inserts instructions to dynamically copy both code segments and variables onto the scratchpad at runtime. We demonstrate that the problem of dynamically overlaying scratchpad is an extension of the global register allocation problem. The overlay problem is solved optimally using ILP formulation techniques. Our approach improves upon the only previously known allocation technique for statically allocating both variables and code segments onto the scratchpad. Experiments report an average reduction of 34% and 18% in the energy consumption and the runtime of the applications, respectively. A minimal increase in code size is also reported.

关键词： Scanning probe microscopy Embedded system Runtime Permission Computer science Algorithm design and analysis Application software Memory management Power system management Energy dissipation

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A Novel Deadlock Avoidance Algorithm and Its hardware Implementation 04

A Novel Deadlock Avoidance Algorithm and Its Hardware Implem...

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Proceedings of the international conference on hardware/software codesign and system synthesis: 2004

作者： Jaehwan Lee Vincent John Mooney III Georgia Institute of Technology

ISBN: (纸本)9781581139372

This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provides a mechanism for very fast and automatic deadlock avoidance in MultiProcessor system-on-a-Chip (MPSoC) with multiple (e.g., 10) processing elements and multiple (e.g., 40) resources. The DAU avoids deadlock by not allowing any grant or request that leads to a deadlock. In case of livelock, the DAU asks one of the processes involved in the livelock to release resource(s) so that the livelock can also be resolved. We simulated two realistic examples that can benefit from the DAU, and demonstrated that the DAU not only avoids deadlock in a few clock cycles but also achieves a 37% speed-up of application execution time over avoiding deadlock in software. Finally, the SoC area overhead due to the DAU is small, under 0.01% in our example.

关键词： Algorithms

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A loop accelerator for low power embedded VLIW processors 04

A loop accelerator for low power embedded VLIW processors

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international conference on hardware/software codesign and system synthesis (CODES)

作者： B. Mathew A. Davis School of Computing University of Utah Salt Lake UT USA

ISBN: (纸本)9781581139372

The high transistor density afforded by modern VLSI processes has enabled the design of embedded processors that use clustered execution units to deliver high levels of performance. However, delivering data to the execution resources in a timely manner remains a major problem that limits ILP. It is particularly significant for embedded systems where memory and power budgets are limited. A distributed address generation and loop acceleration architecture for VLIW processors is presented. This decentralized on-chip memory architecture uses multiple SRAMs to provide high intra-processor bandwidth. Each SRAM has an associated stream address generator capable of implementing a variety of addressing modes in conjunction with a shared loop accelerator. The architecture is extremely useful for generating application specific embedded processors, particularly for processing input data which is organized as a stream. The idea is evaluated in the context of a fine grain VLIW architecture executing complex perception algorithms such as speech and visual feature recognition. Transistor level Spice simulations are used to demonstrate a 159x improvement in the energy delay product when compared to conventional architectures executing the same applications.

关键词： VLIW Very large scale integration Process design Embedded system Distributed power generation Acceleration Memory architecture Bandwidth Random access memory Speech analysis

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Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation 04

Modeling operation and microarchitecture concurrency for com...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Xinping Zhu Wei Qin S. Malik Department of Electrical Engineering Princeton University Princeton NJ USA

ISBN: (纸本)9781581139372

In multiprocessor based SoCs, optimizing the communication architecture is often as important as, if not more than, optimizing the computation architecture. While there are mature platforms and techniques for the modeling and evaluation of computation architectures, the same is not true for the communication architectures. A major challenge in modeling the communication architecture is managing the concurrency at multiple levels: at the operation level, multiple communication operations may be active at any time; at the microarchitecture level, several microarchitectural components may be operating in parallel. Further, it is important to be able to clearly specify how the operation level concurrency maps to the microarchitectural level concurrency. This work presents a modeling methodology and a retargetable simulation framework which fill this gap. This framework seeks to facilitate the design space exploration of the communication sub-system through a rigorous modeling approach based on a formal concurrency model, the operation state machine (OSM). We first introduce the basic notions and concepts of OSM and show by example how this model can be used to represent the inherent concurrency in the architecture and microarchitecture of processors. Then we demonstrate the applicability of OSM in modeling on-chip communication architectures (OCAs) by walking though a router based packet switching network example and a bus example. Due to the fact that the OSM model is naturally suited to handle the operation and microarchitecture level concurrencies of OCAs as well, our OSM-based modeling methodology enables the entire system including both the computation and communication architectures to be modeled in a single OSM framework. This allows us to develop a tool set that can synthesize cycle-accurate system simulators for multi-PE SoC prototypes. To demonstrate the flexibility of this methodology, we choose two distinct system configurations with different types of OCA:

关键词： Microarchitecture Concurrent computing Computer architecture Computational modeling Communication system operations and management Space exploration Network-on-a-chip Legged locomotion Packet switching Network synthesis

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