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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

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A Platform-based SoC hardware/software Co-Design Environment

A Platform-based SoC Hardware/Software Co-Design Environment

引用

The 8th international conference on Computer Supported Cooperative Work in Design(第八届计算机支持的协同工作设计国际会议)(CSCWD2004)

作者： Zhihui Xiong Sikun Li Jihua Chen Dawei Wang School of Computer Science National University of Defense TechnologyChangshaP.R.China410073

ISBN: (纸本)0780379411

This paper presents a Platform-based SoChardware/software co-design environment namedHSCDE. It introduces the overall structure of HSCDE,describes the Platform-based SoC system modelingtechnology, ant algorithm based hardware/softwarepartitioning technology and Hierarchical DirectedAcyclic Graph based performance constraintassignment technology. HSCDE supports Platform-based SoC hardware/software co-design *** supports almost all the design phases from SoCsystem modeling to RTL level SoC system. It dividesSoC hardware/software co-design into system modelinglevel (level 1), virtual components level (level 2) andreal components level (level 3), and it performs the 2mappings among the 3 design levels by DesignPlanning (mapping 1) and Virtual-Real synthesis(mapping 2). We have clone SoC system design for MP3player SoC, MEPG2 player SoC and CDMA wirelesscommunication SoC in HSCDE environment. Resultsshow that HSCDE effectively supports Platform-basedSoC hardware/software co-design methodology;itenhanced system reuse of existing SoC design. Statisticsindicate an average of 10％～25％ revisions on platformtemplates for a new SoC design, and we achievedplatform template reuse ratio by 75％～90％.

关键词： hardware-software codesign system-on-chip directed graphs logic design integrated circuit design SoC hardware-software codesign HSCDE SoC system modeling hardware-software partitioning hierarchical directed acyclic graph performance constraint assignment technology RTL level SoC system virtual components level virtual-real synthesis MP3 player SoC MEPG2 player SoC CDMA wireless communication SoC

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Keynote: cellular handset technology system requirements and integration trends 04

Keynote: cellular handset technology system requirements and...

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Proceedings of the 2nd IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Sven Mattisson Ericsson Mobile Platforms AB Lund Sweden

ISBN: (纸本)9781581139372

In ten years the cellular telephone has evolved from a tool for the professional to an indispensable consumer product with a very high market penetration. At the same time, the handset cost, weight, and standby time have been reduced by more than a factor of ten. These factors have been critical for the success story of the mobile *** technical aspects behind the rapid handset evolution are discussed. In particular, what advances in the radio architecture, for example the zero-IF GSM receiver,the baseband (CMOS) technology, andthe radio system design areasSW-DSP-digital-RF partitioning,linear multi-mode modulation with high linearity requirements,digital leakage issues, andpower consumption limitations in multimedia handsets are discussed with future generation handsets in mind.

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Bluespec system Verilog: efficient, correct RTL from high level specifications

Bluespec System Verilog: efficient, correct RTL from high le...

引用

acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： R. Nikhil Bluespec Inc. Waltham MA USA

Bluespec system Verilog is an EDL toolset for ASIC and FPGA design offering significantly higher productivity via a radically different approach to high-level synthesis. Many other attempts at high-level synthesis have tried to move the design language towards a more software-like specification of the behavior of the intended hardware. By means of code samples, demonstrations and measured results, we illustrate how Bluespec system Verilog, in an environment familiar to hardware designers, can significantly improve productivity without compromising generated hardware quality.

关键词： hardware Productivity High level synthesis Atomic measurements Application specific integrated circuits Field programmable gate arrays Flow graphs Scheduling Logic design Predictive models

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Bluespec system Verilog: efficient, correct RTL from high level specifications 04

Bluespec System Verilog: efficient, correct RTL from high le...

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Proceedings of the Second acm/IEEE international conference on Formal Methods and Models for Co-Design

ISBN: (纸本)9780780385092

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Checkers for systemC designs

Checkers for SystemC designs

引用

acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： D. Grobe R. Drechsler Institute of Computer Science University of Bremen Bremen Germany Institute of Computer Science University of Berman Bremen Germany

Today's complex systems are modeled on a high level of abstraction. In this context, C/C++-based description languages, like systemC, become very important. The modeling features of systemC enable adequate levels of abstraction, hardware/software integration and fast executable specifications. Using the systemC design methodology, a system is partitioned into hardware and software. Then the modules are refined down to the implementation. Besides efficient modeling, the correct functional behavior is very important. Already today up to 80% of the overall design costs are due to verification. As the complete system cannot be formally verified, checking of the functional behavior during operation has to be considered. In this paper an approach is presented that allows to check temporal properties for a systemC design not only during simulation, but also after fabrication inform of an on-line test. The method translates the properties into synthesizable systemC instructions. By this, the properties can be checked like HDL assertions during simulation and after production since they can be synthesized together with the system. The proposed approach enables a concise circuit and system verification methodology.

关键词： Circuit simulation Circuit synthesis Design methodology Costs Fabrication Circuit testing system testing hardware design languages Production systems Circuits and systems

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First IEEE/acm/IFIP international conference on hardware/ software codesign and systems synthesis (IEEE Cat. No.03TH8721)

First IEEE/ACM/IFIP International Conference on Hardware/ So...

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international conference on hardware/software codesign and system synthesis (CODES)

The following topics are dealt with: hardware-software codesign; system synthesis; architectural exploration; system simulation; system modeling; real time services; OS services; embedded software; embedded hardware; on-chip communication; scheduling techniques; system verification; system analysis; system design; performance evaluation; and compiler optimizations.

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Extending the systemC synthesis subset by object-oriented features

Extending the SystemC synthesis subset by object-oriented fe...

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1st IEEE/acm/IFIP international conference on Hardward/software codesign and system synthesis

作者： Grimpe, E Oppenheimer, F OFFIS Res Inst D-26121 Oldenburg Germany

ISBN: (纸本)1581137427

In this article we present an approach to object-oriented hardware design and synthesis based on systemC. We will give an introduction to an extended systemC synthesis subset which we propose, and;in particular, its object-oriented features. We will also briefly outline our basic synthesis concepts for object-oriented hardware specifications. Finally we will present some examples for the application of the extended synthesis subset, which are directly processable by a first synthesis tool prototype which we have developed for this purpose.

关键词： systemC C/C plus plus based design hardware description language hardware synthesis system level design object-orientation high-level synthesis

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RTOS scheduling in transaction level models 03

RTOS scheduling in transaction level models

引用

1st IEEE/acm/IFIP international conference on Hardward/software codesign and system synthesis

作者： Yu, HB Gerstlauer, A Gajski, D Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92697 USA

ISBN: (纸本)1581137427

Raising the level of abstraction in system design promises to enable faster exploration of the design space at early stages. While scheduling decision for embedded software has great impact on system performance, it's much desired that the designer can select the right scheduling algorithm at high abstraction levels so as to save him from the error-prone and time consuming task of tuning code delays or task priority assignments at the final stage of system design. In this paper we tackle this problem by introducing a RTOS model and an approach to refine any unscheduled transaction level model (TLM) to a TLM with RTOS scheduling support. The refinement process provides a useful tool to the system designer to quickly evaluate different dynamic scheduling algorithms and make the optimal choice at the early stage of system design.

关键词： RTOS SpecC system design model

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hardware support for real-time operating systems

Hardware support for real-time operating systems

引用

1st IEEE/acm/IFIP international conference on Hardward/software codesign and system synthesis

作者： Kohout, P Ganesh, B Jacob, B EVI Technol LLC Columbia MD 21046 USA

ISBN: (纸本)1581137427

The growing complexity of embedded applications and pressure on time-to-market has resulted in the increasing use of embedded real-time operating systems. Unfortunately, RTOSes can introduce a significant performance degradation. This paper presents the Real-Time Task Manager (RTM)-a processor extension that minimizes the performance drawbacks associated with RTOSes. The RTM accomplishes this by supporting, in hardware, a few of the common RTOS operations that are performance bottlenecks: task scheduling, time management, and event management. By exploiting the inherent parallelism of these operations, the RTM completes them in constant time, thereby significantly reducing RTOS overhead. It decreases both the processor time used by the RTOS and the maximum response time by an order of magnitude.

关键词： RTOS hardware software codesign

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Pareto-optimization-based run-time task scheduling for embedded systems 03

Pareto-optimization-based run-time task scheduling for embed...

引用

1st IEEE/acm/IFIP international conference on Hardward/software codesign and system synthesis

作者： Yang, P Catthoor, F IMEC B-3001 Louvain Belgium

ISBN: (纸本)1581137427

Pareto-set-based optimization can be found in several different areas of embedded system design. One example is task scheduling, where different task mapping and ordering choices for a target platform will lead to different performance/cost tradeoffs. To explore this design space at run-time, a fast and effective heuristic is needed. We have modeled the problem as the well known Multiple Choice Knapsack Problem(MCKP) and have developed a fast greedy heuristic for the run-time task scheduling. To show the effectiveness of our algorithm, examples from randomly generated task graphs and realistic applications are studied. Compared to the optimal dynamic programming solver, the heuristic is more than ten times faster while the result is less than 5% away from the optimum. Moreover, due to its iterative feature, the algorithm is well suitable to be used as an on-line algorithm.

关键词： Pareto optimization scheduling embedded system lowpower

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