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Pareto-optimization-based run-time task scheduling for embedded systems 03

Pareto-optimization-based run-time task scheduling for embed...

引用

1st IEEE/acm/IFIP international conference on Hardward/software codesign and system synthesis

作者： Yang, P Catthoor, F IMEC B-3001 Louvain Belgium

ISBN: (纸本)1581137427

Pareto-set-based optimization can be found in several different areas of embedded system design. One example is task scheduling, where different task mapping and ordering choices for a target platform will lead to different performance/cost tradeoffs. To explore this design space at run-time, a fast and effective heuristic is needed. We have modeled the problem as the well known Multiple Choice Knapsack Problem(MCKP) and have developed a fast greedy heuristic for the run-time task scheduling. To show the effectiveness of our algorithm, examples from randomly generated task graphs and realistic applications are studied. Compared to the optimal dynamic programming solver, the heuristic is more than ten times faster while the result is less than 5% away from the optimum. Moreover, due to its iterative feature, the algorithm is well suitable to be used as an on-line algorithm.

关键词： Pareto optimization scheduling embedded system lowpower

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synthesis of Real-Time Embedded software with Local and Global Deadlines 03

Synthesis of Real-Time Embedded Software with Local and Glob...

引用

First IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2003

作者： Hsiung, Pao-Ann Lin, Cheng-Yi Department of Computer Science National Chung Cheng University Chiayi-621 Taiwan

ISBN: (纸本)1581137427

Current methods cannot synthesize real-time embedded software applications when the global deadline of a task is shorter than the total of all local deadlines along a critical path in the task. This creates unnecessary modeling limitations which directly affect the types of systems synthesizable. We propose a quasi-dynamic scheduling algorithm for simultaneously guaranteeing both local and global deadlines, while satisfying all precedence constraints among sub-tasks and among tasks. Through this scheduling procedure, we are able to formally synthesize real-time embedded software from a network of Real-Time Petri Nets specification. Application examples, including a driver for the Master/Slave role switch in Bluetooth wireless communication devices, are given to illustrate the feasibility of the scheduling algorithm.

关键词： Embedded systems

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A low-cost and low-power multi-standard video encoder

A low-cost and low-power multi-standard video encoder

引用

1st IEEE/acm/IFIP international conference on Hardward/software codesign and system synthesis

作者： Llopis, RP Sethuraman, R Pinto, CA Peters, H Maul, S Oosterhuis, M Philips Res Labs NL-5656 AA Eindhoven Netherlands

ISBN: (纸本)1581137427

Video encoders are an important IP block in mobile multimedia systems. In this paper, we describe a low-cost low-power multi-standard (MPEG4, JPEG, and H.263) video/image encoder. The low-cost and low-power aspects are achieved by the right choice of algorithms and architectures. In the algorithm front, an embedded compression technique for reducing the size of loop memory has enabled a single-chip low-cost realization of the encoder. In the architectural front, an efficient hardware-software partitioning has contributed to the design of a low-power encoder. Further, the hardware components that accelerate the kernels of encoding are implemented as application specific instruction-set processors (ASIPs) thereby providing flexibility to address multi-standard encoding. The power and area estimates for the encoder for QCIF@15fps in 0.18mum CMOS technology are 30mW and 20mm(2) respectively including the loop memory.

关键词： video encoder multi-standard low-power low-cost ASIPs hardware/software partitioning

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A low-cost memory architecture with NAND XIP for mobile embedded systems

A low-cost memory architecture with NAND XIP for mobile embe...

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1st IEEE/acm/IFIP international conference on Hardward/software codesign and system synthesis

作者： Park, C Seo, J Bae, S Kim, H Kim, S Kim, B Samsung Elect Co Ltd Software Ctr Seoul 135893 South Korea

ISBN: (纸本)1581137427

NAND flash memory has become an indispensable component in mobile embedded systems because of its versatile features such as non-volatility, solid-state reliability, low cost and high density. Even though NAND flash memory is gaining popularity as data storage, it can be also exploited as code memory for XIP (execute-in-place). In this paper, we present a new memory architecture which incorporates NAND flash memory into an existing memory hierarchy for code execution. The usefulness of the proposed approach is demonstrated with real embedded workloads on a real prototyping board.

关键词： memory architecture NAND XIP priority-based caching

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Deriving process networks from weakly dynamic applications in system-level design

Deriving process networks from weakly dynamic applications i...

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1st IEEE/acm/IFIP international conference on Hardward/software codesign and system synthesis

作者： Stefanov, T Deprettere, E Leiden Univ Leiden Inst Adv Comp Sci Leiden Embedded Res Ctr NL-2300 RA Leiden Netherlands

ISBN: (纸本)1581137427

We present an approach to the automatic derivation of executable Process Network specifications from Weakly Dynamic Applications. We introduce the notions of Dynamic Single Assignment Code, Approximated Dependence Graph, and Linearly Bounded Sets to model and capture weakly dynamic (data-dependent) behavior of applications at the task-level of abstraction. Process Networks are simple parallel processing models that match the emerging multi-processor architectures in the sense that the mapping of Process Network specifications of applications onto multi-processor architectures can be done in a systematic and transparent way.

关键词： system-level design heterogeneous embedded systems kahn process networks weakly dynamic applications

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SEAS: A system for early analysis of SoCs

SEAS: A system for early analysis of SoCs

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1st IEEE/acm/IFIP international conference on Hardward/software codesign and system synthesis

作者： Bergamaschi, RA Shin, YS Dhanwada, N Bhattacharya, S Dougherty, WE Nair, I Darringer, J Paliwal, S IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

ISBN: (纸本)1581137427

systems-on-chip (SoC) continue to be very complex to design and verify, despite extensive component reuse. Although reusable components are pre-designed and pre-verified, when they are assembled in an SoC there is no guarantee that the whole system will behave as expected from a performance, cost and integration point of view. In many cases this is because of faulty early design decisions regarding the architecture, core selection, floorplanning, etc. This paper presents a system for early analysis of SoCs which helps designers make early design decisions regarding performance, area, timing and power;and allows them to quickly evaluate cross-domain effects, such as the effect that an architectural decision may have on the performance and chip area.

关键词： design analysis design space exploration performance power floorplanning

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Synthesizing operating system based device drivers in embedded systems

Synthesizing operating system based device drivers in embedd...

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1st IEEE/acm/IFIP international conference on Hardward/software codesign and system synthesis

作者： Wang, SJ Malik, S Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)1581137427

This paper presents a correct-by-construction synthesis method for generating operating system based device drivers from a formally specified device behavior model. Existing driver development is largely manual using an ad-hoc design methodology. Consequently, this task is error prone and becomes a bottleneck in embedded system design methodology. Our solution to this problem starts by accurately specifying device access behavior with a formal model, viz. extended event driven finite state machines. We state easy to check soundness conditions on the model that subsequently guarantee properties such as bounded execution time and deadlock-free behavior. We design a deadlock-free resource accessing scheme for our device access model. Finally, we synthesize an operating system (OS) based event processing mechanism, which is the core of the device driver, using a disciplined methodology that assures the correctness of the resulting driver. We validate our synthesis method using two case studies: an infrared port and the USB device controller for an SA I 100 based handheld. Besides assuring a correct-by -construction driver, the size of the specification is 70% smaller than a manually written driver, which is a strong indicator of improved design productivity.

关键词： correct-by-construction device driver operating system based software synthesis embedded system software

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Architecture and synthesis for Multi-Cycle On-Chip Communication

Architecture and Synthesis for Multi-Cycle On-Chip Communica...

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First IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2003

作者： Cong, Jason Fan, Yiping Man, Guoling Yang, Xun Zhang, Zhiru Computer Science Department Univ. of California Los Angeles Los Angeles CA 90095 United States

The design methodologies to address the multi-cycle on-chip communication problems were discussed. A regular distributed register (RDR) micro-architecture which offers high regularity and direct support of multi-cycle communication was proposed. A set of novel architectural synthesis algorithms to efficiently synthesize behavior-level design onto the RDR architecture was developed. After comparing architectural synthesis for multi-cycle communication (MCAS) with conventional architectural synthesis flow, results achieved clock improvement of 33% and a total latency improvement of 24% on average.

关键词： Microprocessor chips

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A Case Study of Mapping a software-Defined Radio (SDR) Application on a Reconfigurable DSP Core 03

A Case Study of Mapping a Software-Defined Radio (SDR) Appli...

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First IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2003

作者： Mohebbi, Behzad Filho, Eliseu Chavez Maestre, Rafael Davies, Mark Kurdahi, Fadi J. Morpho Technologies Inc. 19772 Mac Arthur Blvd. Irvine CA 92612 EECS Department University of California Irvine CA 92697

ISBN: (纸本)9781581137422

We present a case study involving the implementation of a complete Wideband CDMA (WCDMA) digital receiver part of an AMR channel onto a reconfigurable core. WCDMA is one of the two major standards for the third generation (3G) cellular systems. Traditionally most of the receiver components were confined to ASIC implementation for performance, size and power consumption reasons. The MSI reconfigurable DSP core provides both a microprocessor and reconfigurable fabric as well as a variety of peripherals. The various functions of the receiver were mapped onto different core components. The complete system was tested both in simulation as well as on a hardware platform comprising a silicon implementation of the MSI DSP core.

关键词： software engineering

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Early Estimation of the Size of VHDL Projects

Early Estimation of the Size of VHDL Projects

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First IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2003

作者： Fornaciari, William Salice, Fabio Scarpazza, Daniele Paolo Politecnico di Milano - DEI Piazza Leonardo da Vinci 32 Milano Italy

The analysis of the amount of human resources required to complete a project is felt as a critical issue in any company of the electronics industry. In particular, early estimating the effort involved in a development process is a key requirement for any cost-driven system-level design decision. In this paper, we present a methodology to predict the final size of a VHDL project on the basis of a high-level description, obtaining a significant indication about the development effort. The methodology is the composition of a number of specialized models, tailored to estimate the size of specific component types. Models were trained and tested on two disjoint and large sets of real VHDL projects. Quality-of-result indicators show that the methodology is both accurate and robust.

关键词： Computer hardware description languages

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