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system-level design tools: Who needs them, who has them, and how much should they cost?

System-level design tools: Who needs them, who has them, and...

引用

1st IEEE/acm/IFIP international conference on Hardward/software codesign and system synthesis

作者： Bergamaschi, R Martin, G Smith, G Paulin, P Fordham, R Hardee, P Bailey, B IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA

ISBN: (纸本)1581137427

CAD vendors are always faced with the question of what tools to develop and how much can they charge for them. Designers on the other hand have real problems to solve and before investing in tools they have to assess how much a given tool will actually save them. CAD vendors and designers have to estimate the savings in design time and cost that a tool may provide and compare that with the existing way of doing things, to determine if the investment in tool creation is justified. For example, if a misguided architectural decision causes weeks of delay because of missing performance targets, then a tool for early architectural analysis may be very valuable. system-level design poses exactly these types of questions because it involves optimizations and analyses across many domains, from software, to architecture, to cycle-time, and is done very early in the design cycle where it has a profound impact. How much improvement in productivity and overall design quality (e.g., timing, area, and power) can be attained by current and future generations of system-level tools? If designers believe such improvements can be obtained, are they prepared to pay the appropriate price for the tools? Or do system-level CAD vendors still need to make believers out of designers? This panel will bring together industry experts to review the current and future industry needs for system-level design technologies as well as discuss how much saving in design time and cost such tools can hope to achieve and whether the designers believe the price is right for the return they can get.

关键词： Computer aided design

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Design Space Exploration of a hardware-software Co-designed GF(2 m) Galois Field Processor for Forward Error Correction and Cryptography 03

Design Space Exploration of a Hardware-Software Co-designed ...

引用

First IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis, CODES+ISSS 2003

作者： Lim, Wei-Ming Benaissa, M. University of Sheffield Department of Electronic Engineering Mappin Street Sheffield S1 3JD United Kingdom

ISBN: (纸本)9781581137422

This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m), such as RS and BCH codes, Elliptic Curve Cryptography and the AES. Complexities of flexible implementations of different applications on a same computation architecture can be migrated to software during design time. However, the underlying GF(2m) arithmetic architecture needs to be designed with software programmability (or reconfigurability) in mind. We describe novel reconfigurable subword parallel GF(2m) arithmetic architectures designed with an associated instruction set architecture for different applications over GF(2m) and same applications with differing parameters. Design space exploration is carried out with two simple parameters P and Q which can be changed at design time and will affect the performance of different applications and flexibility of the final implementation. We show implementation results given for an FPGA prototype of the processor and programmed for RS and BCH coding, AES and elliptic curve cryptography with differing parameters. Complexity figures and configuration overheads for subword parallel GF(2m) arithmetic architectures are also estimated and discussed.

关键词： Program processors

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Dynamic hardware/software partitioning: A first approach

Dynamic hardware/software partitioning: A first approach

引用

40th Design Automation conference

作者： Stitt, G Lysecky, R Vahid, F Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)1581136889

Partitioning an application among software running on a microprocessor and hardware co-processors in on-chip configurable logic has been shown to improve performance and energy consumption in embedded systems. Meanwhile, dynamic software optimization methods have shown the usefulness and feasibility of runtime program optimization, but those optimizations do not. achieve as much as partitioning. We introduce a first approach to dynamic hardware/software partitioning. We describe our system architecture and initial on-chip tools, including profiler, decompiler, synthesis, and placement and routing tools for a simplified configurable logic fabric, able to perform dynamic partitioning of real benchmarks. We show speedups averaging 2.6 for five benchmarks taken from Powerstone, NetBench, and our own benchmarks.

关键词： hardware/software partitioning FPGA synthesis platforms system-on-a-chip dynamic optimization codesign self-improving chips embedded systems

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From use cases to system implementation: Statechart based co-design 1

From use cases to system implementation: Statechart based co...

引用

1st acm/IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE 03)

作者： Gomes, L Costa, A Univ Nova Lisboa Fac Ciencias & Tecnol Dept Elect Engn P-2825 Monte De Caparica Portugal

ISBN: (纸本)0769519237

This paper proposes a methodology for embedded systems co-design, based on statechart models. The process starts with grabbing the system functionalities through use cases. A set of procedures addressing the implementation of Statechart models is presented. The main goal of this set of procedures is to lift the structuring mechanisms presented in statecharts to the top level. In this sense, the complexity of statechart implementation will be similar to the complexity of communicating concurrent state machines and the platforms selected to support implementation will not need to have specific capabilities to directly support the structuring mechanisms of Harel's statecharts. As a consequence, full direct implementation of statecharts is possible considering different types of implementation platforms, ranging from hardware-centric or software-centric to hardware-software partitioning through codesign techniques.

关键词： Computational modeling Computer aided software engineering Concurrent computing Data processing Embedded computing Embedded software Embedded system hardware Real time systems Unified modeling language

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Bus architecture synthesis for hardware-software co-design of deep submicron systems on chip

Bus architecture synthesis for hardware-software co-design o...

引用

21st international conference on Computer Design

作者： Thepayasuwan, N Damle, V Doboli, A SUNY Stony Brook Dept Elect & Comp Engn Stony Brook NY 11794 USA

ISBN: (纸本)0769520251

system level design always has a disadvantage of not possessing detailed knowledge of the communication sub-system. This is a crucial issue for system-on-Chip design, where uncertainty in communication by very deep submicron effects cannot be neglected. This paper presents a bus architecture (BA) synthesis algorithm for designing the communication sub-system of an SoC. The algorithm is part of a hardware-software codesign methodology for resource constrained embedded applications. BA synthesis includes finding the bus topology, and routing the individual buses so that various constraints, like bus length, topology complexity, potential for communication conflicts over time, are addressed. The paper presents BA synthesis results for a network processor, and a JPEG SoC.

关键词： Integrated circuit layout

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Driving agenda for systems research

Driving agenda for systems research

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： N. Dutt University of California Irvine

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SoC synthesis with automatic hardware software interface generation 16

SoC synthesis with automatic hardware software interface gen...

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16th international conference on VLSI Design/2nd international conference on Embedded systems Design

作者： Singh, A Chhabra, A Gangwar, A Dwivedi, BK Balakrishnan, M Kumar, A Tejas Networks Bangalore Karnataka India

ISBN: (纸本)0769518680

Design of efficient system-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardware in order to meet the cost as well as the performance constraints. However, faster time to market requires automation of synthesis of these code segments of the application from high level specification such as C alongwith its interfaces. Such synthesis system should be able to generate hardware which is easily plug-gable in various types of architectures, as well as augment the application code to automatically take advantage of this new hardware component. In this paper we address this problem and present an approach for complete SoC synthesis. We automatically generate synthesizable VHDL for the compute intensive part of the application alongwith necessary interfaces. Our approach is generic in the sense that it supports various processors and buses by keeping a generic hardware interface on one end and a dedicated one on the other The generated hardware can be used in a tightly or loosely coupled manner in terms of memory and register communication. We present the effectiveness of this approach for some commonly used image processing. spatial filter applications.

关键词： Automation Computer architecture Computer interfaces Costs hardware Image processing Registers Spatial filters system-on-a-chip Time to market

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Bridging CSP and C++ with selective formalism and executable specifications 1

Bridging CSP and C++ with selective formalism and executable...

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1st acm/IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE 03)

作者： Gardner, WB Univ Guelph Dept Comp & Informat Sci Guelph ON Canada

ISBN: (纸本)0769519237

CSP (Communicating Sequential Processes) is a useful algebraic notation for creating a hierarchical behavioural specification for concurrent systems, due to its formal interprocess synchronization and communication semantics. CSP specifications are amenable to simulation and formal verification by model-checking tools. To overcome the drawback that CSP is neither a full-featured nor popular programming language, an approach called "selective formalism" allows the use of CSP to be limited to specifying the control portion of a system, while the rest of its functionality is supplied in the form of C++ modules. These are activated through association with abstract events in the CSP specification. The target system is constructed using a framework called CSP++, which automatically translates CSP specifications into C++, thereby making CSP directly executable. Thus a bridge is built that allows a formal method to be combined with a popular programming language. It is believed that this methodology can be extended to hardware/software codesign.

关键词： Automatic control Communication system control Computational modeling Computer languages Concurrent computing Control systems Formal verification hardware Information science Spine

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BHDL: circuit design in B 3

BHDL: circuit design in B

引用

3rd international conference on Application of Concurrency to system Design

作者： Aljer, A Devienne, P Tison, S Boulanger, JL Mariano, G Lab Informat Fondamentale Lille Lille France

ISBN: (纸本)0769518877

The main goal of this project is to provide a method of correct design of digital circuit. It combines the advantages of VHDL, the well-known language of circuit design, with the Power of B method that guarantees the correct design (w.r.t. a formal specification). This allows avoiding the design test since it is "correct by proven construction". Furthermore, this project provides a tool, called BHDL, with a graphical interface for creating, editing, viewing and proving modular hardware architectures.

关键词： Circuit simulation Circuit synthesis Circuit testing Computer languages Design methodology Digital circuits Formal specifications hardware software prototyping software tools

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Task graph extraction for embedded system synthesis 16

Task graph extraction for embedded system synthesis

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16th international conference on VLSI Design/2nd international conference on Embedded systems Design

作者： Vallerio, KS Jha, NK Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)0769518680

Consumer demand and improvements in hardware have caused distributed real-time embedded systems to rapidly increase in complexity. As a result, designers faced with time-to-market constraints are forced to rely on intelligent design tools to enable them to keep up with demand These tools are continually being used earlier in the design process when the design is at higher levels of abstraction. At the highest level of abstraction are hardware/software co-synthesis tools which take a system specification as input. Although many embedded systems are described in C, the system specifications for many of these tools are often in the form of one or more task graphs. These tools are very effective at solving the co-synthesis problem using task graphs but require that designers manually transform the specification from C code to task graphs, a tedious and error-prone job. The task graph extraction tool described in this paper reduces the potential for error and the time required to design an embedded system by automating the task graph extraction process. Such a tool can drastically improve designer productivity. As far as we know, this is the first tool of its kind. It has been made available on the web.

关键词： Embedded software Embedded system Field programmable gate arrays hardware Job design Process design Productivity Real time systems software libraries software tools

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