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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

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The future of system-level design: can we find the right solutions to the right problems at the right time?

The future of system-level design: can we find the right sol...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： R. Bergamaschi W. Wolf J. Kouloheris G. Martin R. Ernst K. Vissers IBM Research NY USA Cadence Labs Berkeley CA USA Princeton University NJ USA TU Braunschweig Germany UC Berkeley CA USA

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Extending the systemC synthesis subset by object-oriented features 03

Extending the SystemC synthesis subset by object-oriented fe...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： E. Grimpe F. Oppenheimer OFFIS Research Institute Oldenburg Germany

ISBN: (纸本)9781581137422

In this article we present an approach to object-oriented hardware design and synthesis based on systemC. We give an introduction to an extended systemC synthesis subset which we propose, and, in particular, its object-oriented features. We will also briefly outline our basic synthesis concepts for object-oriented hardware specifications. Finally, we present some examples for the application of the extended synthesis subset, which are directly processable by a first synthesis tool prototype which we have developed for this purpose.

关键词： Object oriented modeling system-level design Embedded system hardware design languages Productivity Embedded software Prototypes Logic design Real time systems High level synthesis

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High speed GAML-based phylogenetic tree reconstruction using HW/SW codesign 2

High speed GAML-based phylogenetic tree reconstruction using...

引用

2nd international Computational systems Bioinformatics conference

作者： Mak, TST Lam, KP Chinese Univ Hong Kong Dept Syst Engn & Engn Management Sha Tin 100083 Peoples R China

ISBN: (纸本)0769520006

Heuristics for reconstructing the phylogenetic tree of DNA sequences based on maximum likelihood are computationally expensive. The tree evaluation function that calculates the likelihood value for each tree topology dominates the time in searching the optimal tree. We developed a hybrid hardware/software (HW/SW) system for solving the phylogenetic tree reconstruction problem using the Genetic Algorithm for Maximum Likelihood (GAML) approach. The GAML is partitioned into a genetic algorithm (GA) and a fitness evaluation function, with the SW handling the GA and the HW evaluating the maximum likelihood function. This approach exploits the flexibility of software and the speed up of high performance hardware. An efficient Field Programmable Gate Arrays (FPGA) implementation for the required computation on evolution tree topology fitness evaluation is proposed The complete high-level digital design is developed and Xilinx's Java-based JBits toolkit is used for constructing a BRAM interface for digital process synchronization control and GA chromosomes transmission between a workstation and the Xilinx Virtex-800 FPGA Processor. This implementation provides approximately 30 to 100 times in speedup improvement when compared to a software solution.

关键词： DNA sequences

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Transaction level modeling: an overview 03

Transaction level modeling: an overview

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： L. Cai D. Gajski Center for Embedded Computer Systems University of California Irvine Irvine CA USA

ISBN: (纸本)9781581137422

Recently, the transaction-level modeling has been widely referred to in system-level design community. However, the transaction-level models (TLMs) are not well defined and the usage of TLMs in the existing design domains, namely modeling, validation, refinement, exploration, and synthesis, is not well coordinated. This paper introduces a TLM taxonomy and compares the benefits of TLMs' use.

关键词： Computer architecture Permission Embedded computing system-level design system-on-a-chip Productivity Computational modeling Tail

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High level verification of control intensive systems using predicate abstraction 1

High level verification of control intensive systems using p...

引用

1st acm/IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE 03)

作者： Clarke, E Grumberg, O Talupur, M Wang, D Carnegie Mellon Univ Pittsburgh PA 15217 USA

ISBN: (纸本)0769519237

Predicate abstraction has been widely used for model checking hardware/software systems. However, for control intensive systems, existing predicate abstraction techniques can potentially result in a blowup of the size of the abstract model. We deal with this problem by retaining important control variables in the abstract model. By this method we avoid having to introduce an unreasonable number of predicates to simulate the behavior of the control variables. We also show how to improve predicate abstraction by extracting useful information from a high level representation of hardware/software systems. This technique works by first extracting relevant branch conditions. These branch conditions are used to invalidate spurious abstract counterexamples through a new counterexample-based lazy refinement algorithm. Experimental results are included to demonstrate the effectiveness of our methods.

关键词： Cities and towns Concrete Contracts Control system synthesis Control systems Data mining hardware Logic design Size control software systems

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A codesigned on-chip logic minimizer 03

A codesigned on-chip logic minimizer

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international conference on hardware/software codesign and system synthesis (CODES)

作者： R. Lysecky F. Vahid Department of Computer Science and Engineering University of California Riverside USA Department of Computer Science and Engineering University of California Irvine Riverside USA

ISBN: (纸本)9781581137422

Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic use in embedded systems, including network route table reduction, network access control list table reduction, and dynamic hardware/software partitioning. These new uses require logic minimization to run dynamically as part of an embedded system's active operation. Performing such dynamic logic minimization on-chip greatly reduces system complexity and security versus an approach that involves communication with a desktop logic minimizer. An on-chip minimizer must be exceptionally lean yet yield good enough results. Previous software-only on-chip minimizer results have been good, but we show that a codesigned minimizer can be much better, executing nearly 8 times faster and consuming nearly 60% less energy, while yielding identical results.

关键词： Logic Minimization Boolean functions Embedded system Control system synthesis Network synthesis Access control hardware Embedded software system-on-a-chip

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Deriving process networks from weakly dynamic applications in system-level design 03

Deriving process networks from weakly dynamic applications i...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： T. Stefanov E. Deprettere Leiden Embedded Research Center Leiden Institute of Advanced Computer Science Leiden University Netherlands

ISBN: (纸本)9781581137422

We present an approach to the automatic derivation of executable process network specifications from weakly dynamic applications. We introduce the notions of dynamic single assignment code, approximated dependence graph, and linearly bounded sets to model and capture weakly dynamic (data-dependent) behavior of applications at the task-level of abstraction. Process networks are simple parallel processing models that match the emerging multiprocessor architectures in the sense that the mapping of process network specifications of applications onto multiprocessor architectures can be done in a systematic and transparent way.

关键词： Intelligent networks system-level design Mathematical model Computational modeling Application software Concurrent computing Computer networks Computer science Embedded computing Design automation

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Early estimation of the size of VHDL projects 03

Early estimation of the size of VHDL projects

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： W. Fornaciari F. Salice D.P. Scarpazza Politecnico di Milano Milan Italy

ISBN: (纸本)9781581137422

The analysis of the amount of human resources required to complete a project is felt as a critical issue in any company of the electronics industry. In particular, early estimation of the effort involved in a development process is a key requirement for any cost-driven system-level design decision. In this paper, we present a methodology to predict the final size of a VHDL project on the basis of a high-level description, obtaining a significant indication about the development effort. The methodology is the composition of a number of specialized models, tailored to estimate the size of specific component types. Models were trained and tested on two disjoint and large sets of real VHDL projects. Quality-of-result indicators show that the methodology is both accurate and robust.

关键词： Costs Humans system-level design Testing Embedded system Permission Robustness hardware software engineering software measurement

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Verification of design decisions in ForSyDe 03

Verification of design decisions in ForSyDe

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international conference on hardware/software codesign and system synthesis (CODES)

作者： T. Raudvere I. Sander Ashish Kumar Singh A. Jantsch Royal Institute of Technology Stockholm Sweden

ISBN: (纸本)9781581137422

The ForSyDe methodology has been developed for system level design. Starting with a formal specification model that captures the functionality of the system at a high abstraction level, it provides formal design transformation methods for a transparent refinement process of the specification model into an implementation model that is optimized for synthesis. A transformation may be semantic preserving or a design decision. The latter modifies the semantics of the system level description and changes the meaning of the model. The main contribution of this paper is the incorporation of model checking to verify that refined system blocks satisfy the design specification. We illustrate the translation of the ForSyDe code to the SMV language and the verification of local design decisions with a case study of a ForSyDe equalizer model.

关键词： Design methodology Application software Computer architecture Permission Formal specifications Design optimization Equalizers Logic design Circuits Embedded system

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Driving forces behind SoC development 03

Driving forces behind SoC development

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international conference on hardware/software codesign and system synthesis (CODES)

作者： M.C. Chian Mindspeed Technologies Sr. VP Core Technology

ISBN: (纸本)9781581137422

In this paper, we examine the vectors of cost, methodology, technology, and their interrelationship in SOC development. We stress that now, more than ever, methodology and technology choices for SoC design and implementation have to be economically driven. If the high mortality rate of small chip companies and depressed earnings of larger ones over the past three years are any indication, we see renewed interest in business fundamentals such as total available market (TAM) and return on investment (ROI). This is perhaps one of the most vivid changes we will all experience in the post bubble era.

关键词： Packaging Design automation Costs Design engineering Strontium Technological innovation system-on-a-chip Stress Companies Investments

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