检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

994 篇 会议
40 篇 期刊文献

馆藏范围

1,034 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

542 篇 工学
- 512 篇 计算机科学与技术...
- 403 篇 软件工程
- 109 篇 电气工程
- 103 篇 电子科学与技术（可...
- 48 篇 信息与通信工程
- 40 篇 控制科学与工程
- 26 篇 机械工程
- 12 篇 建筑学
- 11 篇 动力工程及工程热...
- 7 篇 材料科学与工程（可...
- 6 篇 光学工程
- 6 篇 安全科学与工程
- 5 篇 土木工程
- 4 篇 生物工程
- 3 篇 生物医学工程（可授...
- 2 篇 力学（可授工学、理...
- 2 篇 仪器科学与技术
- 2 篇 化学工程与技术
113 篇 理学
- 68 篇 数学
- 46 篇 系统科学
- 11 篇 物理学
- 8 篇 统计学（可授理学、...
- 4 篇 生物学
67 篇 管理学
- 56 篇 管理科学与工程(可...
- 20 篇 工商管理
- 12 篇 图书情报与档案管...
10 篇 法学
- 6 篇 社会学
- 4 篇 法学
7 篇 艺术学
- 7 篇 设计学（可授艺术学...
5 篇 经济学
- 5 篇 应用经济学
1 篇 医学

主题

207 篇 hardware
113 篇 computer archite...
94 篇 embedded system
67 篇 application soft...
60 篇 embedded systems
60 篇 permission
55 篇 system-on-a-chip
51 篇 computational mo...
48 篇 field programmab...
47 篇 algorithm design...
47 篇 software
41 篇 energy consumpti...
40 篇 costs
37 篇 system-on-chip
34 篇 real time system...
34 篇 space exploratio...
33 篇 embedded softwar...
32 篇 timing
32 篇 high level synth...
31 篇 system-level des...

机构

8 篇 center for embed...
8 篇 department of el...
7 篇 univ calif river...
7 篇 department of co...
6 篇 school of comput...
6 篇 arizona state un...
6 篇 center for embed...
6 篇 institute for in...
5 篇 princeton univ d...
5 篇 school of inform...
5 篇 philips research...
5 篇 university of er...
5 篇 nec laboratories...
4 篇 natl taiwan univ...
4 篇 department of co...
4 篇 politecn torino ...
4 篇 carnegie mellon ...
4 篇 tu braunschweig
4 篇 university of ca...
4 篇 university of do...

作者

9 篇 sri parameswaran
9 篇 ogras umit y.
9 篇 nikil dutt
8 篇 leupers rainer
7 篇 rolf ernst
7 篇 teich juergen
7 篇 robert p. dick
7 篇 parameswaran sri
6 篇 jiang wei
6 篇 dick robert p.
6 篇 dutt nikil
6 篇 mitra tulika
6 篇 rainer leupers
6 篇 andreas gerstlau...
6 篇 jha niraj k.
5 篇 pasricha sudeep
5 篇 gerd ascheid
5 篇 greg stitt
5 篇 jinyu zhan
5 篇 ernst rolf

语言

1,033 篇 英文
1 篇 其他

检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

共 1034 条记录，以下是81-90 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

2016 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2016

2016 International Conference on Hardware/Software Codesign ...

引用

2016 international conference on hardware/software codesign and system synthesis, CODES+ISSS 2016

ISBN: (纸本)9781450330503

The proceedings contain 37 papers. The topics discussed include: a practical methodology to validate the statistical behavior of bloom filters;scalable and realistic benchmark synthesis for efficient NoC performance evaluation: a complex network analysis approach;an accurate and flexible early memory system power evaluation approach using a microcomponent method;how to enable software isolation and boost system performance with sub-block erase over 3D flash memory;realizing erase-free SLC flash memory with rewritable programming design;an overview of micron's automata processor;enabling the high level synthesis of data analytics accelerators;and big data analytics on heterogeneous accelerator architectures.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Proceedings of the 9th international Workshop on hardware and Architectural Support for Security and Privacy, HASP 2020

Proceedings of the 9th International Workshop on Hardware an...

引用

9th international Workshop on hardware and Architectural Support for Security and Privacy, HASP 2020, in conjunction with the 53rd international Symposium on Microarchitecture, MICRO 2020

ISBN: (纸本)9781450388986

The proceedings contain 8 papers. The topics discussed include: implementing the draft RISC-V scalar cryptography extensions;analysis and hardware optimization of lattice post-quantum cryptography workloads;uncovering hidden instructions in Armv8-A implementations;applying the principle of least privilege to system management interrupt handlers with the Intel SMI Transfer monitor;FPGA bitstream modification with interconnect in mind;consider hardware-enhanced defenses for rootkit attacks;defending direct memory access with CHERI capabilities;and SoK: opportunities for software-hardware-security codesign for next generation secure computing.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Toward Evaluating High-Level synthesis Portability and Performance between Intel and Xilinx FPGAs 21

Toward Evaluating High-Level Synthesis Portability and Perfo...

引用

2021 international Workshop on OpenCL, IWOCL 2021

作者： Cabrera, Anthony M Young, Aaron R Lambert, Jacob Xiao, Zhili An, Amy Lee, Seyong Jin, Zheming Kim, Jungwon Buhler, Jeremy Chamberlain, Roger D Vetter, Jeffrey S Oak Ridge National Laboratory Oak RidgeTN United States University of Oregon EugeneOR United States Washington University in St. Louis St. LouisMO United States

ISBN: (纸本)9781450390330

Offloading computation from a CPU to a hardware accelerator is becoming a more common solution for improving performance because traditional gains enabled by Moore's law and Dennard scaling have slowed. GPUs are often used as hardware accelerators, but field-programmable gate arrays (FPGAs) are gaining traction. FPGAs are beneficial because they allow hardware specific to a particular application to be created. However, they are notoriously difficult to program. To this end, two of the main FPGA manufacturers, Intel and Xilinx, have created tools and frameworks that enable the use of higher level languages to design FPGA hardware. Although Xilinx kernels can be designed by using C/C++, both Intel and Xilinx support the use of OpenCL C to architect FPGA hardware. However, not much is known about the portability and performance between these two device families other than the fact that it is theoretically possible to synthesize a kernel meant for Intel to Xilinx and vice versa. In this work, we evaluate the portability and performance of Intel and Xilinx kernels. We use OpenCL C implementations of a subset of the Rodinia benchmarking suite that were designed for an Intel FPGA and make the necessary modifications to create synthesizable OpenCL C kernels for a Xilinx FPGA. We find that the difficulty of porting certain kernel optimizations varies, depending on the construct. Once the minimum amount of modifications is made to create synthesizable hardware for the Xilinx platform, more nontrivial work is needed to improve performance. However, we find that constructs that are known to be performant for an FPGA should improve performance regardless of the platform;the difficulty comes in deciding how to invoke certain kernel optimizations while also abiding by the constraints enforced by a given platform's hardware compiler. © 2021 acm.

关键词： High level synthesis

来源：评论

学校读者我要写书评

暂无评论

FPGA HW/SW codesign approach for real-time image processing using HLS 1

FPGA HW/SW codesign approach for real-time image processing ...

引用

1st international conference on Communications, Control systems and Signal Processing, CCSSP 2020

作者： Azzaz, Mohamed Salah Maali, Abdelmadjd Kaibou, Redouane Kakouche, Ibrahim Saad, Mohamed Hamil, Hocine Ecole Militaire Polytechnique Laboratoire SEN Algiers Algeria Mouloud Mammeri University LAMPA Laboratory Tizi-Ouzou15000 Algeria

ISBN: (纸本)9781728158358

Real-time constraint is one of the most common challenges found in many critical embedded applications, namely image and video processing. However, software tools such as Matlab and general purpose microprocessor are not suitable for deals with such a problem. Recently, FPGA reconfigurable circuit with its HLS software tools is become a very promising technology to be widely used in many applications encompassing all aspects and requirements of embedded system. This paper presents the implementation of morphological image operation including dilation, erosion and linear filtering. The implementation method is based on hardware/software (HW/SW) codesign approach using High Level synthesis (HLS) tools, Xilinx Vivado 15.2 and SDK 15.2. Zedboard FPGA platform with Zynq device is used for this work in which is connected to a PC through an Ethernet link. Captured image by Webcam is transmitted to the FPGA for processing and will be then returned to the PC to be displayed on the IHM interface, in real-time. Experimental results demonstrate the feasibility of the proposed approach and it can be extended for other applications. © 2020 IEEE.

关键词： Field programmable gate arrays (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays 18

Real-time Scheduling of I/O Transfers for Massively Parallel...

引用

18th acm-IEEE international conference on Formal Methods and Models for system Design (MEMOCODE)

作者： Walter, Dominik Witterauf, Michael Teich, Juergen Friedrich Alexander Univ Erlangen Nurnberg FAU Hardware Software Codesign Dept Comp Sci Erlangen Germany

ISBN: (纸本)9781728191485

A fundamental problem of massively parallel accelerator architectures is the management of typically small peripheral I/O buffers that decouple the accelerator from an external memory. Very often, these buffers cannot store the entire input and output data of one execution and must be updated, i.e., filled or drained, frequently. Moreover, if a processor array performs either a read on an empty bank or a write on a full bank, it must interrupt its execution immediately until the corresponding data transfer between the accelerator and an external memory has been carried out. As a consequence, the timing predictability of the array execution might be impaired. Therefore, a precise analysis of a schedule for all data transfers is inevitable. Moreover, as it is prohibitive to store all data transfers entirely within the accelerator itself, we must determine and schedule all necessary data transfers dynamically at runtime. In this paper, we present an approach to characterize all necessary data transfers and to issue them in time so that the peripheral I/O buffers never run full or empty. Here, it is shown first that a deadline for each data transfer can be derived from a given loop schedule resulting in a traditional task scheduling problem. Unfortunately, however, standard real-time scheduling techniques such as earliest deadline first (EDF) cannot be applied here, as each data transfer must not be interrupted and even existing non-preemptive variants of EDF are known to be prone to timing anomalies. As a solution, we present a strictly non-work-conserving variant of EDF together with an efficient schedulability test for periodic loop executions. In an experimental section, the scheduling approach is applied to a randomly generated set of loop programs observing that our algorithm is able to feasibly schedule 95% of the theoretically schedulable problem instances. Altogether, we provide a fully timing-predictable buffer management for massively parallel processor array

关键词： Data transfer

来源：评论

学校读者我要写书评

暂无评论

A New hardware Trojan Design: Distinguishing Between Trigger Inputs and Functional Inputs Is Difficult: Work-in-Progress

A New Hardware Trojan Design: Distinguishing Between Trigger...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Ge, Minghui Zhang, Ying Li, Sen Yao, Jiaqi Mao, Zhiming Chen, Xin Nanjing Univ Aeronaut & Astronaut NUAA Dept Elect & Informat Engn EIE Nanjing Peoples R China

ISBN: (纸本)9781728191980

In this paper, we propose a new hardware Trojan Design. This design makes all HT trigger inputs have the same impact as functional inputs on output signals. It is difficult to distinguish between trigger inputs and functional inputs. Simultaneously, trigger inputs will not be identified as redundant inputs. This approach can defeat the existing detection methods which identify weakly affecting and red Cant trigger inputs across multiple sequential levels. The proposed HT has stealthiness and general applicability.

关键词： hardware trojan trigger inputs functional inputs

来源：评论

学校读者我要写书评

暂无评论

Work-in-Progress: Fine-Grained Acceleration using Runtime Integrated Custom Execution (RICE)

Work-in-Progress: Fine-Grained Acceleration using Runtime In...

引用

Embedded systems Week / Int Conf on Compilers, Architecture, and synthesis for Embedded systems (CASES) / international conference on hardware/software codesign and system synthesis (CODES+ISSS) / Int Conf on Embedded software (EMSOFT)

作者： Pakanati, Leela McMichen, John T. Estrada, Zachary Rose Hulman Inst Technol Terre Haute IN 47803 USA

ISBN: (纸本)9781450369251

Runtime Integrated Custom Execution (RICE) relocates traditional peripheral reconfigurable acceleration devices into the pipeline of the processor. This relocation unlocks fine-grained acceleration previously impeded by communication overhead to a peripheral accelerator. Preliminary simulation results on a subset of the PARSEC benchmark suite shows promise for RICE in HPC applications.

关键词： RISC-V hardware Acceleration FPGA hardware-software Co-Design Gem5 PARSEC

来源：评论

学校读者我要写书评

暂无评论

Techniques for Design Analysis and Modification Based on ASAP Model Work-in-Progress

Techniques for Design Analysis and Modification Based on ASA...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Du, Ke Domas, Stephane Lenczner, Michel Univ Bourgogne Franche Comte FEMTO ST Inst UMR 6174 CNRS Belfort France

ISBN: (纸本)9781728191980

In the domain of model-based design, the main challenge is to provide a model with a set of conditions and algorithms to ensure that the designed system produces correct results. A dataflow based model called Actors with Stretchable Access Patterns (ASAP) has been recently proposed, which takes the behavior of functional blocks on real architectures, especially FPGAs, into account. In this work, we present the framework of techniques to analyze the correctness of designs based on the ASAP model and to determine a set of modifications that must be applied to faulty cases to ensure the conformance of all actors. The principles are illustrated by a realistic application.

关键词： ASAP FPGA model-based design system analysis EDA

来源：评论

学校读者我要写书评

暂无评论

Model Stealing Defense with Hybrid Fuzzy Models: Work-in-Progress

Model Stealing Defense with Hybrid Fuzzy Models: Work-in-Pro...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Gong, Zicheng Jiang, Wei Zhan, Jinyu Song, Ziwei Univ Elect Sci & Technol China Sch Informat & Software Engn Chengdu Peoples R China

ISBN: (纸本)9781728191980

With increasing applications of Deep Neural Networks (DNNs) to edge computing systems, security issues have received more attentions. Particularly, model stealing attack is one of the biggest challenge to the privacy of models. To defend against model stealing attack, we propose a novel protection architecture with fuzzy models. Each fuzzy model is designed to generale wrong predictions corresponding to a particular category. In addition, we design a special voting strategy to eliminate the systemic errors, which can destroy the dark knowledge in predictions at the same time. Preliminary experiments show that our method substantially decreases the clone model's accuracy (up to 20%) without loss of inference accuracy for benign users.

关键词： Deep neural networks

来源：评论

学校读者我要写书评

暂无评论

Attention-Based Secure Feature Extraction in Near Sensor Processing: Work-in-Progress

Attention-Based Secure Feature Extraction in Near Sensor Pro...

引用

international conference on hardware/software codesign and system synthesis (CODES+ISSS)

作者： Bhowmik, Pankaj Pantho, Md Jubaer Hossain Saha, Sujan Kumar Bobda, Christophe Univ Florida Dept Elect & Comp Engn Gainesville FL 32611 USA

ISBN: (纸本)9781728191980

This paper presents a secure hardware architecture of an image sensor to accelerate feature extraction using region-level parallelism. For each logical region, the design includes a region processing unit (RPU) with an attention module (AM). The AM activates the processing in the RPU if there are no spatiotemporal redundancies. It reduces power consumption and data volume by utilizing the concepts of predictive coding. Also, every RPU has a crypto-core driven by the AM to withstand against adversaries. Simulation results show we can save 89.70% power with a significant speedup.

关键词： Pixel Level Processing SIFT Attention Module Image Sensor hardware security FPGA ASIC

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共104页 << < 5 6 7 8 9 10 11 12 13 14 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：