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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

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A case study of mapping a software-defined radio (SDR) application on a reconfigurable DSP core

A case study of mapping a software-defined radio (SDR) appli...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： Behzad Mohebbi E.C. Filho F.J. Kurdahi Morpho Technologies Inc Irvine CA

We present a case study involving the implementation of a complete Wideband CDMA (WCDMA) digital receiver part of an AMR channel onto a reconfigurable core. WCDMA is one of the two major standards for the third generation (3G) cellular systems. Traditionally most of the receiver components were confined to ASIC implementation for performance, size and power consumption reasons. The MS1 reconfigurable DSP core provides both a microprocessor and reconfigurable fabric as well as a variety of peripherals. The various functions of the receiver were mapped onto different core components. The complete system was tested both in simulation as well as on a hardware platform comprising a silicon implementation of the MS1 DSP core.

关键词： Application software Digital signal processing Multiaccess communication Wideband Receivers Application specific integrated circuits Energy consumption Microprocessors Fabrics system testing

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Design technology challenges for system and chip level designs in very deep submicron technologies 03

Design technology challenges for system and chip level desig...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： J. Lin National Semiconductor Israel

ISBN: (纸本)9781581137422

With very deep submicron process technologies, previously ignorable phenomena now have great impact on the robustness of IC designs. At the same time, the smaller feature sizes also enable an exponential increase in number of functions (or transistor count) available on chip. Complexity in process technology and design is widening the Design Technology gap, which, if not addressed properly, will threaten the continuation of process scaling and the industry's ability to benefit from it. The complexity of process and design technology, its impact on new designs, new products development and future solutions will be discussed in this presentation.

关键词： Process design Circuit testing Robustness Product design Product development Biographies Electronics industry Logic design Logic testing Design engineering

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Design optimization of mixed time/event-triggered distributed embedded systems 03

Design optimization of mixed time/event-triggered distribute...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： T. Pop P. Eles Z. Peng Department of Computer and Information Science Linköping University Sweden

ISBN: (纸本)9781581137422

Distributed embedded systems implemented with mixed, event-triggered task sets, which communicate over bus protocols consisting of both static and dynamic phases, are emerging as the new standard in application areas such as automotive electronics. In a previous paper, we developed a holistic timing analysis and scheduling approach for this category of systems. Based on this result, new design problems are solved, which we identified as characteristic for such hybrid systems: partitioning of the system functionality into time-triggered and event-triggered domains and the optimization of parameters corresponding to the communication protocol. We addressed both problems in the context of a heuristic which performs mapping and scheduling of the system functionality. We demonstrate the efficiency of the proposed technique with extensive experiments.

关键词： Design optimization Embedded system Scheduling Automotive engineering Distributed computing Embedded computing Timing Protocols Algorithm design and analysis Real time systems

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A low-cost memory architecture with NAND XIP for mobile embedded systems 03

A low-cost memory architecture with NAND XIP for mobile embe...

引用

international conference on hardware/software codesign and system synthesis (CODES)

作者： C. Park Jaeyu Seo Sunghwan Bae Hyojun Kim Shinhan Kim Bumsoo Kim Software Center Samsung Electronics Company Limited Seoul South Korea

ISBN: (纸本)9781581137422

NAND flash memory has become an indispensable component in mobile embedded systems because of its versatile features such as nonvolatility, solid-state reliability, low cost and high density. Even though NAND flash memory is gaining popularity as data storage, it can be also exploited as code memory for XIP (execute-in-place). In this paper, we present a new memory architecture in which incorporates NAND flash memory into an existing memory hierarchy for code execution. The usefulness of the proposed approach is demonstrated with real embedded workloads on a real prototyping board.

关键词： Memory architecture Embedded system Energy consumption Costs Random access memory Flash memory Delay Solid state circuits Memory management Cache storage

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Security wrappers and power analysis for SoC technology

Security wrappers and power analysis for SoC technology

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international conference on hardware/software codesign and system synthesis (CODES)

作者： C.H. Gebotys Y. Zhang Department of Electrical and Computer Engineering University of Waterloo Canada

Future wireless Internet enabled services will be increasingly powerful supporting many more applications including one of the most crucial, security. Although SoCs offer more resistance to bus probing attacks, power/EM attacks on cores and network snooping attacks by malicious code are relevant. This paper presents a methodology for security on NoC at both the network level (or transport layer) and at the core level (or application layer) is proposed. For the first time a low cost security wrapper design is presented, which prevents unencrypted keys from leaving the cores and NoC. This is crucial to prevent untrusted software on or off the NoC from gaining access to keys. At the core level (application layer) power analysis attacks are examined for the first time for parallel and adiabatic architectural cores. With the emergence of secure IP cores in the market, a security methodology for designing NoCs is crucial for supporting future wireless Internet enabled devices.

关键词： Network-on-a-chip system-on-a-chip Protection Communication system security Application software Algorithm design and analysis hardware Power system security Design methodology Circuits

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SEAS: a system for early analysis of SoCs

SEAS: a system for early analysis of SoCs

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international conference on hardware/software codesign and system synthesis (CODES)

作者： R.A. Bergamaschi Youngsoo Shin N. Dhanwada S. Bhattacharya W.E. Dougherty I. Nair J. Darringer R. Paliwal IBM T.J. Watson Research Center Yorktown Heights NY USA IBM EDA Laboratory Fishkill NY USA

systems-on-chip (SoC) continue to be very complex to design and verify, despite extensive component reuse. Although reusable components are predesigned and preverified, when they are assembled in an SoC there is no guarantee that the whole system will behave as expected from a performance, cost and integration point of view. In many cases this is because of faulty early design decisions regarding the architecture, core selection, floorplanning, etc. This paper presents a system for early analysis of SoCs which helps designers make early decisions regarding performance, area, timing and power; and allows them to quickly evaluate cross-domain effects, such as the effect that an architectural decision may have on the performance and chip area.

关键词： Timing Algorithm design and analysis Performance analysis Application specific integrated circuits Process design Permission Logic design DH-HEMTs Electronic design automation and methodology Laboratories

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hardware support for real-time operating systems 03

Hardware support for real-time operating systems

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international conference on hardware/software codesign and system synthesis (CODES)

作者： P. Kohout B. Ganesh B. Jacob EVI Technology LLC Columbia Maryland Department of Electrical and Computer Engineering University of Maryland College Park Maryland USA EVI Technology Limited Liability Company ColumbiA MD USA Department of Electrical and Computer Engineering University of Maryland College Park Maryland

ISBN: (纸本)9781581137422

The growing complexity of embedded applications and pressure on time-to-market has resulted in the increasing use of embedded real-time operating systems. Unfortunately, RTOSes can introduce a significant performance degradation. The paper presents the Real-Time Task Manager (RTM) - a processor extension that minimizes the performance drawbacks associated with RTOSes. The RTM accomplishes this by supporting, in hardware, a few of the common RTOS operations that are performance bottlenecks: task scheduling, time management, and event management. By exploiting the inherent parallelism of these operations, the RTM completes them in constant time, thereby significantly reducing RTOS overhead. It decreases both the processor time used by the RTOS and the maximum response time by an order of magnitude.

关键词： hardware Real time systems Operating systems Delay Parallel processing Degradation Processor scheduling Multitasking Costs Time to market

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Tracking object life cycle for leakage energy optimization 03

Tracking object life cycle for leakage energy optimization

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international conference on hardware/software codesign and system synthesis (CODES)

作者： G. Chen N. Vijaykrishnan M. Kandemir M.J. Irwin M. Wolczko Department of Computer Science and Engineering Pennsylvania State University University Park PA USA Sun Microsystems Inc. Mountain View CA USA

ISBN: (纸本)9781581137422

The focus of this work is on utilizing the state of objects during their lifespan in optimizing the leakage energy consumed in the data caches when executing embedded Java applications. Our analysis reveals that a major portion of the leakage energy is actually wasted in retaining the objects beyond their last use. In order to eliminate this wastage, we investigate three approaches that use the garbage collector, escape analysis and last use analysis for reducing leakage energy. Finally, we track the access gap between successive object accesses to reduce leakage energy of live objects. A combination of these schemes is shown to provide 21% data cache leakage energy reduction in our default configuration.

关键词： Energy consumption Java Permission Voltage Turning Computer science Data engineering Power engineering and energy Application software hardware

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Synthesizing operating system based device drivers in embedded systems 03

Synthesizing operating system based device drivers in embedd...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Shaojie Wang Sharad Malik Department of Electrical Engineering Princeton University Princeton NJ USA

ISBN: (纸本)1581137427

This paper presents a correct-by-construction synthesis method for generating operating system based device drivers from a formally specified device behavior model. Existing driver development is largely manual using an ad-hoc design methodology. Consequently, this task is error prone and becomes a bottleneck in embedded system design methodology. Our solution to this problem starts by accurately specifying device access behavior with a formal model, viz. extended event driven finite state machines. We state easy check soundness conditions on the model that subsequently guarantee properties such as bounded execution time and deadlock-free behavior. We design a deadlock-free resource accessing scheme for our device access model. Finally, we synthesize an operating system (OS) based event processing mechanism, which is the core of the device driver, using a disciplined methodology that assures the correctness of the resulting driver. We validate our synthesis method using two case studies: an infrared port and the USB device controller for an SA1100 based handheld. Besides assuring a correct-by-construction driver, the size of the specification is 70% smaller than a manually written driver, which is a strong indicator of improved design productivity.

关键词： Operating systems Embedded system Productivity software engineering Design methodology system recovery Control system synthesis Automatic programming Permission Formal specifications

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Session details: Advances in system modeling 03

Session details: Advances in system modeling

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Proceedings of the 1st IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Hiroto Yasuura Kyushu University

No abstract available.

ISBN: (纸本)9781581137422

No abstract available.

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