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A multiobjective optimization model for exploring multiprocessor mappings of process networks 03

A multiobjective optimization model for exploring multiproce...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： C. Erbas S.C. Erbas A.D. Pimentel Department of Computer Science University of Amsterdam Amsterdam Netherlands Department of Stochastics RWTH Aachen University of Technology Aachen Germany

ISBN: (纸本)9781581137422

In the Sesame framework, we develop a modeling and simulation environment for the efficient design space exploration of heterogeneous embedded systems. Since Sesame recognizes separate application and architecture models within a single system simulation, it needs an explicit mapping step to relate these models for co-simulation. So far in Sesame, the mapping decision as been assumed to be made by an experienced designer, intuitively. However, this assumption is increasingly becoming inappropriate for the following reasons: already the realistic systems are far too complex for making intuitive decisions at an early design stage where the design space is very large. Likely, these systems will get even more complex in the near future. Besides, there exist multiple criteria to consider, like processing times, power consumption and cost of the architecture, which make the decision problem even harder. The mapping decision problem is formulated as a multiobjective combinatorial optimization problem. For a solution approach, an optimization software tool, implementing an evolutionary algorithm from the literature, has been developed to achieve a set of best alternative mapping decisions under multiple criteria. In a case study, we have used our optimization tool to obtain a set of mapping decisions, some of which were further evaluated by the Sesame simulation framework.

关键词： Space exploration Embedded system Application software Signal design Computer science Computational modeling Energy consumption Costs Power system modeling Computer architecture

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Design space minimization with timing and code size optimization for embedded DSP

Design space minimization with timing and code size optimiza...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： Qingfeng Zhuge Zili Shao Bin Xiao W.H.-M. Sha Department of Computer Science University of Texas at Dallas Richardson Texas Department of Computer Science University of Texas at Dallas Richardson Texas USA

One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integrated Framework for Design Optimization and Space Minimization (IDOM) towards finding the minimum configuration satisfying timing and code size constraints. We show an effective way to reduce the design space to be explored through the study of the fundamental properties and relations among multiple design parameters, such as retiming value, unfolding factor, timing, and code size. Theories are presented to produce a small set of feasible design choices with provable quality. IDOM algorithm is proposed to generate high-quality design by integrating performance and code size optimization techniques. The experimental results on a set of DSP benchmarks show the efficiency and effectiveness of the IDOM algorithm. It constantly generates the minimal configuration for all the benchmarks. The cost of design space exploration using IDOM is only 3% of that using the standard method.

关键词： Timing Design optimization Digital signal processing Space exploration High level synthesis Algorithm design and analysis Costs

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Architecture and synthesis for multi-cycle on-chip communication 03

Architecture and synthesis for multi-cycle on-chip communica...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： J. Cong Yiping Fan Guoling Han Xun Yang Zhiru Zhang Computer Science Department University of California Los Angeles Los Angeles CA USA

ISBN: (纸本)9781581137422

There are two important infection points in the development of deep submicron (DSM) process technologies. The first point is when the average interconnect delay exceeds the gate delay, which happened during mid 1990s and led to the so-called timing closure problem. The second point is when single-cycle full chip synchronization is no longer possible, which is about to happen soon. It can be shown that, even with the aggressive interconnect optimization techniques (e.g., buffer insertion and wire-sizing), 5 clock cycles are still needed to go from corner-to-corner for the die of 28.3 mm /spl times/ 28.3 mm in the 0.07 /spl mu/m technology generation, assuming a 5.63 GHz clock by 2006 predicted in ITRS'01 (2001). This clearly suggests that multi-cycle on-chip communication is a necessity in multi-gigahertz synchronous designs. However, it is not supported in the current design tools and methodologies, as most of these implicitly assume that full chip synchronization in a single clock cycle is feasible. Our contributions are as follows: (i) we propose a regular distributed register (RDR) microarchitecture which offers high regularity and direct support of multi-cycle communication; (ii) we develop a set of novel architectural synthesis algorithms to efficiently synthesize behavior-level designs onto the RDR architecture.

关键词： Clocks Registers Design methodology Computer architecture Delay Distributed computing Integrated circuit interconnections Synchronization Signal design Communication system control

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system-level design tools: who needs them, who has them, and how much should they cost?

System-level design tools: who needs them, who has them, and...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： R. Bergamaschi G. Martin G. Smith P. Paulin R. Fordham P. Hardee B. Bailey CoWare Inc. USA Design Verification and Test Division Mentor Graphics USA IBM Thomas J. Watson Research Center Yorktown Heights NY USA Cadence Berkeley Laboratories Berkeley CA USA Gartner Dataquest Inc. USA STMicroelectronics Inc. Canada Motorola Global Software Group USA

CAD vendors are always faced with the question of what tools to develop and how much can they charge for them. Designers on the other hand have real problems to solve and before investing in tools they have to assess how much a given tool will actually save them. CAD vendors and designers have to estimate the savings in design time and cost that a tool may provide and compare that with the existing way of doing things, to determine if the investment in tool creation is justified. For example, if a misguided architectural decision causes weeks of delay because of missing performance targets, then a tool for early architectural analysis may be very valuable. system-level design poses exactly these types of questions because it involves optimizations and analyses across many domains, from software, to architecture, to cycle-time, and is done very early in the design cycle where it has a profound impact. This panel will bring together industry experts to review the current and future industry needs for system-level design technologies as well as discuss how much saving in design time and cost such tools can hope to achieve and whether the designers believe the price is right for the return they can get.

关键词： system-level design Costs Design automation Superluminescent diodes Companies Performance analysis Mathematical model Investments Design engineering software performance

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First results with eBlocks: embedded systems building blocks 03

First results with eBlocks: embedded systems building blocks

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international conference on hardware/software codesign and system synthesis (CODES)

作者： S. Cotterell F. Vahid Walid Najjar H. Hsieh Department of Computer Science and Engineering Center for Embedded Computer Systems at UC lrvine University of California Riverside USA

ISBN: (纸本)9781581137422

We describe our first efforts to develop a set of off-the-shelf hardware components that ordinary people could connect to build a simple but useful class of embedded systems. The class of systems, which we call monitor/control systems, is composed primarily of sensors - light, motion, sound, contact, and other types - and output devices - light-emitting diodes, beeping speakers, or even electric relays that control electric appliances like lamps. For example, one monitor/control system would detect if a house's garage door was open at night, and would blink a LED inside the house to alert the homeowner this normally undesirable situation. Today, configuring even the most basic monitor/control system requires knowledge of electronics and programming. We seek to create a set of building blocks, which we call eBlocks, which would enable someone with no knowledge of electronics or programming to be able to build simple but useful monitor/control systems. We are creating eBlocks largely by incorporating intelligence into previously dumb sensors and output devices, and by developing a set of standards and methods that enable eBlocks to work together seamlessly when connected. eBlocks have only recently become possible due to the extremely low cost, low power, and small size of embedded microprocessors. We describe our first results of creating a basic class of eBlocks, Boolean eBlocks, that from a user's perspective transmit or receive only "yes" or "no" signals. We discuss the internal eBlock design, eBlock system design issues and decisions, and several eBlock-based systems designed by ourselves and by undergraduate students.

关键词： Embedded system Control systems Monitoring Motion control Lighting control Light emitting diodes Intelligent sensors hardware Sensor systems Acoustic sensors

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A fast parallel Reed-Solomon decoder on a reconfigurable architecture 03

A fast parallel Reed-Solomon decoder on a reconfigurable arc...

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international conference on hardware/software codesign and system synthesis (CODES)

作者： A. Koohi Nader Bagherzadeh Chengzi Pan EECS Department University of California Irvine USA

ISBN: (纸本)9781581137422

This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targeting on streamed applications such as multimedia and DSP. Numerous modifications of the first-generation of the architecture have made a scalable computation and communication intensive architecture capable of extracting parallelisms of fine grain in instruction level. Many algorithms and the whole digital video broadcasting base-band receiver as well, have been mapped onto the second architecture with impressive performance. The mapping of a Reed-Solomon decoder proposed in the paper highly parallelizes all of its sub-algorithms, including Syndrome Computation, Berlekamp Algorithm, Chein Search, and Error Value Computation, in a SIMD fashion. The mapping is tested on a cycle-accurate simulator, "Mulate", and the performance is encouragingly better than other architectures. The decoding speed of the RS (255,239,16) decoder using two different methods of GF multiplication can be 1.319 Gbps and 2.534 Gbps, respectively. Furthermore, since there is no functionality specifically tailored to Reed-Solomon decoder, the result has demonstrated the capability of MorphoSys architecture to extracting instruction level parallelism from streamed applications.

关键词： Reed-Solomon codes Decoding Reconfigurable architectures Concurrent computing Computer architecture Streaming media Parallel processing Application software Digital signal processing Computer aided instruction

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A new reactive processor with architectural support for control dominated embedded systems 16

A new reactive processor with architectural support for cont...

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16th international conference on VLSI Design/2nd international conference on Embedded systems Design

作者： Roop, PS Salcic, Z Biglari-Abhari, M Bigdeli, A Univ Auckland Dept EEE Auckland 1 New Zealand

ISBN: (纸本)0769518680

Control dominated embedded systems, have to be designed for fast reaction to asynchronous external events occurring in the environment. Such systems must be able to perform signal emission, signal polling, preemption and priority resolution efficiently. Current microprocessors and microcontrollers, however, have no direct support for such tasks and employ indirect mechanisms such as polling (via a port) and interrupts. In this paper we propose a new processor core having architectural support for reactivity at the instruction level. The new processor core (called REFLIX) is an extension of an existing open source processor (FLIX) core with additional instructions to support reactivity. Initial benchmarking results (for some control dominated programs) show that. REFLIX performs, on an average, 5.92 times faster compared to FLIX and has 77% code size reduction when compared to some conventional processors.

关键词： Application software Communication system control Control system synthesis Control systems Embedded system hardware Microcontrollers Microprocessors Signal processing Signal resolution

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A Scalable Application-Specific Processor synthesis Methodology

A Scalable Application-Specific Processor Synthesis Methodol...

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IEEE/acm international conference on Computer Aided Design ICCAD 2003: IEEE/acm Digest of Technical Papers

作者： Sun, Fei Ravi, Srivaths Raghunathan, Anand Jha, Niraj K. Department of Electrical Engineering Princeton University Princeton NJ 08544 United States NEC Laboratories America Princeton NJ 08540 United States

Custom processors based on application-specific or domain-specific instruction sets are gaining popularity, and are often used to implement critical architectural blocks in complex system-on-chips. While several advances have been made in custom processor architectures, tools, and design methodologies, designers are still required to manually perform some critical tasks, such as selection of the custom instructions best suited to the given application and design constraints. We present a scalable methodology for the synthesis of a custom processor from an embedded software program. A key feature of the proposed methodology is its scalability, which is achieved by exploiting the structured, hierarchical nature of large software programs. We motivate the need for such a methodology, and describe the algorithms used for the critical steps, including hardware resource budgeting, local optimizations, and global exploration. Our methodology utilizes the concept of "soft" instruction templates, which can be adapted by adding operations to them or deleting operations from them at any time during the design space exploration process, allowing for global design decisions to be interleaved with fine-grained optimizations. We have integrated our methodology in an open source compiler, and verified it using a commercial extensible processor. Experiments with several benchmarks indicate that our methodology can effectively tackle large programs. It resulted in the synthesis of high-quality custom processors that demonstrated an average speedup of 2.61X and a maximum speedup of 6.32X. The CPU times required for custom processor synthesis were quite small, indicating that the proposed techniques can be applied to embedded software programs of significant complexity.

关键词： Application specific integrated circuits

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Industry best practices in embedded software 03

Industry best practices in embedded software

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Proceedings of the 1st IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Raul Camposano Mark Underseth Faraydon Karim Synopsys Inc. S2Technologies Cardiff CA ST Microelectronics

software is a growing part of the embedded systems industry in a range of applications. This session features presenters from automotive, wireless, and medical devices companies to share their experiences in developin...

ISBN: (纸本)9781581137422

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Polychrony for formal refinement-checking in a system-level design methodology 3

Polychrony for formal refinement-checking in a system-level ...

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3rd international conference on Application of Concurrency to system Design

作者： Talpin, JP Le Guernic, P Shukla, SK Gupta, R Doucet, F IRISA INRIA Rennes France

ISBN: (纸本)0769518877

The productivity gap incurred by the rising complexity of system-on-chip design have necessitated newer design paradigms to be introduced based on system-level design languages. A gating factors for widespread adoption of these new paradigms is a lack of formal tool support of refinement based design. A system level representations may be refined manually (in absence of adequate behavioral synthesis algorithms and tools) to obtain an, implementation, but proving that the lower level representation preserves the correctness proved at higher level models is still an unsolved problem. We address the issue of formal refinement proofs between design abstraction levels using the concepts of polychronous design. Refinement of synchronous high-level designs. into globally asynchronous and locally synchronous architectures is formally supported in this methodology. The polychronous (i.e. multi-clocked) model of, the SIGNAL design language offers formal support for the capture of behavioral abstractions for both very,high-level system descriptions (e.g. systemC/SPECC) and behavioral-level IP components (e.g. VHDL). Its platform, POLYCHRONY, provides models and methods for a rapid, refinement-based, integration and a formal conformance-checking of GALS hardware/software architectures. We demonstrates the effectiveness of our approach by the experimental, comparative, case study of an even-parity checker design in SPECC. It highlights the benefits of the formal models, methods and tools provided in POLYCHRONY, in representing functional, architectural, communication and implementation abstractions of the design, and the successive refinements.

关键词： Concurrent computing system-level design

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