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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

共 1035 条记录，以下是921-930 订阅

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Interface synthesis using memory mapping for an FPGA platform

Interface synthesis using memory mapping for an FPGA platfor...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： M. Luthra Sumit Gupta Nikil Dutt Rajesh Gupta A. Nicolau Center for Embedded Computer Systems University of California Irvine USA Department of Computer Science and Engineering University of California San Diego USA

Several system-on-chip (SoC) platforms have recently emerged that use reconfigurable logic (FPGAs) as a programmable coprocessor to reduce the computational load on the main processor core. We present an interface synthesis approach that forms part of our hardware-software codesign methodology for such an FPGA-based platform. The approach is based on a novel memory mapping algorithm that maps data used by both the hardware and the software to shared memories on the reconfigurable fabric. The memory mapping algorithm couples with a high-level synthesis tool and uses scheduling information to map variables, arrays and complex data structures to the shared memories in a way that minimizes the number of registers and multiplexers used in the hardware interface. We also present three software schemes that enable the application software to communicate with this hardware interface. We demonstrate the utility of our approach and study the trade-offs involved using a case study of the codesign of a computationally expensive portion of the MPEG-1 multimedia application on to the Altera Nios platform.

关键词： Field programmable gate arrays hardware Application software system-on-a-chip Reconfigurable logic Coprocessors software algorithms Fabrics Scheduling algorithm High level synthesis

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The future of system-level design: can we find the right solutions to the right problems at the right time? 03

The future of system-level design: can we find the right sol...

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Proceedings of the 1st IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Reinaldo Bergamaschi Grant Martin Wayne Wolf Rolf Ernst Kees Vissers Jack Kouloheris IBM Research NY Cadence Labs Berkeley CA Princeton University NJ TU Braunschweig Germany UC Berkeley CA

ISBN: (纸本)9781581137422

Over the last 15 years we have seen and helped the evolution of design from behavioral modeling to hardware/software co-design, to today's system-level design. Arguably, many of the research efforts on behavioral synthesis, hardware / software co-design, co-simulation etc. have made their way into successful commercial tools, while others went no further than a conference paper. As we continue and expand system-level research with new approaches opening exciting new research avenues, we have an obligation to look back at our successes and failures. Then looking towards the future, we must answer the question: are we solving the right problems with the right solutions at the right time, or should we go back to the drawing board and think of brand new research *** panel will bring together panelists experienced in various aspects of system-level design who will present different views on what this community has achieved over the last 15 years and draw a roadmap for future research.

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Bus architecture synthesis for hardware-software co-design of deep submicron systems on chip

Bus architecture synthesis for hardware-software co-design o...

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IEEE international conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： N. Thepayasuwan Vaishali Damle A. Doboli Department of Electrical and Computer Engineering State University of New York Stony Brook Stony Brook NY USA

system level design always has a disadvantage of not possessing detailed knowledge of the communication subsystem. This is a crucial issue for system-on-chip design, where uncertainty in communication by very deep submicron effects cannot be neglected. We present a bus architecture (BA) synthesis algorithm for designing the communication subsystem of an SoC. The algorithm is part of a hardware-software codesign methodology for resource constrained embedded applications. BA synthesis includes finding the bus topology, and routing the individual buses so that various constraints, like bus length, topology complexity, potential for communication conflicts over time, are addressed. We present BA synthesis results for a network processor, and a JPEG SoC.

关键词： system-on-a-chip Routing Application software Computer architecture system-level design Algorithm design and analysis Network synthesis Network topology Analog-digital conversion Delay

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From use cases to system implementation: statechart based co-design 03

From use cases to system implementation: statechart based co...

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： L. Gomes A. Costa Faculdade de Ciências e Tecnologia Department of Elect. Engineering & UNINOVA Centro de Robótica Inteligente Universidade Nova de Lisboa Portugal

ISBN: (纸本)9780769519234

This paper proposes a methodology for embedded systems co-design, based on statechart models. The process starts with grabbing the system functionalities through use cases. A set of procedures addressing the implementation of statechart models is presented. The main goal of this set of procedures is to lift the structuring mechanisms presented in statecharts to the top level. In this sense, the complexity of statechart implementation will be similar to the complexity of communicating concurrent state machines and the platforms selected to support implementation will not need to have specific capabilities to directly support the structuring mechanisms of Harel's statecharts. As a consequence, full direct implementation of statecharts is possible considering different types of implementation platforms, ranging from hardware-centric or software-centric to hardware-software partitioning through codesign techniques.

关键词： Computer aided software engineering Embedded system hardware Computational modeling Concurrent computing Embedded software Embedded computing Real time systems Data processing Unified modeling language

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A low-cost and low-power multi-standard video encoder 03

A low-cost and low-power multi-standard video encoder

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Proceedings of the 1st IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： R. Peset Llopis R. Sethuraman C. Alba Pinto H. Peters S. Maul M. Oosterhuis Philips Research Laboratories Eindhoven The Netherlands

ISBN: (纸本)9781581137422

Video encoders are an important IP block in mobile multimedia systems. In this paper, we describe a low-cost low-power multi-standard (MPEG4, JPEG, and H.263) video/image encoder. The low-cost and low-power aspects are achieved by the right choice of algorithms and architectures. In the algorithm front, an embedded compression technique for reducing the size of loop memory has enabled a single-chip low-cost realization of the encoder. In the architectural front, an efficient hardware-software partitioning has contributed to the design of a low-power encoder. Further, the hardware components that accelerate the kernels of encoding are implemented as application specific instruction-set processors (ASIPs) thereby providing flexibility to address multi-standard encoding. The power and area estimates for the encoder for [email protected] in 0.18um CMOS technology are 30mW and 20mm2 respectively including the loop memory.

关键词： multi-standard low-cost hardware/software partitioning low-power video encoder ASIPs

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SEAS: a system for early analysis of SoCs 03

SEAS: a system for early analysis of SoCs

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Proceedings of the 1st IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Reinaldo A. Bergamaschi Youngsoo Shin Nagu Dhanwada Subhrajit Bhattacharya William E. Dougherty Indira Nair John Darringer Sarala Paliwal IBM T.J. Watson Research Center Yorktown Heights NY IBM EDA Laboratory Fishkill NY

ISBN: (纸本)9781581137422

systems-on-chip (SoC) continue to be very complex to design and verify, despite extensive component reuse. Although reusable components are pre-designed and pre-verified, when they are assembled in an SoC there is no guarantee that the whole system will behave as expected from a performance, cost and integration point of view. In many cases this is because of faulty early design decisions regarding the architecture, core selection, floorplanning, etc. This paper presents a system for early analysis of SoCs which helps designers make early design decisions regarding performance, area, timing and power; and allows them to quickly evaluate cross-domain effects, such as the effect that an architectural decision may have on the performance and chip area.

关键词： design analysis floorplanning design space exploration power performance

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Bridging CSP and C++ with selective formalism and executable specifications 03

Bridging CSP and C++ with selective formalism and executable...

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： W.B. Gardner Department of Computing & Information Science University of Guelph Guelph ONT Canada

ISBN: (纸本)9780769519234

CSP (communicating sequential processes) is a useful algebraic notation for creating a hierarchical behavioral specification for concurrent systems, due to its formal interprocess synchronization and communication semantics. CSP specifications are amenable to simulation and formal verification by model-checking tools. To overcome the drawback that CSP is neither a full-featured nor popular programming language, an approach called "selective formalism" allows the use of CSP to be limited to specifying the control portion of a system, while the rest of its functionality is supplied in the form of C++ modules. These are activated through association with abstract events in the CSP specification. The target system is constructed using a framework called CSP++, which automatically translates CSP specifications into C++, thereby making CSP directly executable. Thus a bridge is built that allows a formal method to be combined with a popular programming language. It is believed that this methodology can be extended to hardware/software codesign.

关键词： Computer languages hardware Communication system control Automatic control Spine Concurrent computing Information science Computational modeling Formal verification Control systems

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High level verification of control intensive systems using predicate abstraction 03

High level verification of control intensive systems using p...

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acm and IEEE international conference on Formal Methods and Models for Co-Design (MEMOCODE)

作者： E. Clarke O. Grumberg M. Talupur Dong Wang Carnegie Mellon University Pittsburgh PA USA Technion-Israel Institute of Technology Haifa Israel

ISBN: (纸本)9780769519234

Predicate abstraction has been widely used for model checking hardware/software systems. However, for control intensive systems, existing predicate abstraction techniques can potentially result in a blowup of the size of the abstract model. We deal with this problem by retaining important control variables in the abstract model. By this method we avoid having to introduce an unreasonable number of predicates to simulate the behavior of the control variables. We also show how to improve predicate abstraction by extracting useful information from a high level representation of hardware/software systems. This technique works by first extracting relevant branch conditions. These branch conditions are used to invalidate spurious abstract counterexamples through a new counterexample-based lazy refinement algorithm. Experimental results are included to demonstrate the effectiveness of our methods.

关键词： Control systems Concrete software systems hardware Data mining Logic design Cities and towns Control system synthesis Size control Contracts

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system-level design tools: who needs them, who has them, and how much should they cost? 03

System-level design tools: who needs them, who has them, and...

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Proceedings of the 1st IEEE/acm/IFIP international conference on hardware/software codesign and system synthesis

作者： Reinaldo Bergamaschi Grant Martin IBM Yorktown Heights NY Cadence Berkeley Labs Berkeley CA

ISBN: (纸本)9781581137422

CAD vendors are always faced with the question of what tools to develop and how much can they charge for them. Designers on the other hand have real problems to solve and before investing in tools they have to assess how much a given tool will actually save them. CAD vendors and designers have to estimate the savings in design time and cost that a tool may provide and compare that with the existing way of doing things, to determine if the investment in tool creation is justified. For example, if a misguided architectural decision causes weeks of delay because of missing performance targets, then a tool for early architectural analysis may be very valuable. system-level design poses exactly these types of questions because it involves optimizations and analyses across many domains, from software, to architecture, to cycle-time, and is done very early in the design cycle where it has a profound *** much improvement in productivity and overall design quality (e.g., timing, area, and power) can be attained by current and future generations of system-level tools? If designers believe such improvements can be obtained, are they prepared to pay the appropriate price for the tools? Or do system-level CAD vendors still need to make believers out of designers?This panel will bring together industry experts to review the current and future industry needs for system-level design technologies as well as discuss how much saving in design time and cost such tools can hope to achieve and whether the designers believe the price is right for the return they can get.

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A scalable application-specific processor synthesis methodology 03

A scalable application-specific processor synthesis methodol...

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IEEE international conference on Computer-Aided Design

作者： F. Sun S. Ravi A. Raghunathan N.K. Jha Department of Electrical Engineering Princeton University Princeton NJ USA NEC Laboratories of America Inc. Princeton NJ USA

ISBN: (纸本)9781581137620

Custom processors based on application-specific or domain-specific instruction sets are gaining popularity, and are often used to implement critical architectural blocks in complex system-on-chips. While several advances have been made in custom processor architectures, tools, and design methodologies, designers are still required to manually perform some critical tasks, such as selection of the custom instructions best suited to the given application and design constraints. We present a scalable methodology for the synthesis of a custom processor from an embedded software program. A key feature of the proposed methodology is its scalability, which is achieved by exploiting the structured, hierarchical nature of large software programs. We motivate the need for such a methodology, and describe the algorithms used for the critical steps, including hardware resource budgeting, local optimizations, and global exploration. Our methodology utilizes the concept of "soft" instruction templates, which can be adapted by adding operations to them or deleting operations from them at any time during the design space exploration process, allowing for global design decisions to be interleaved with fine-grained optimizations. We have integrated our methodology in an open source compiler, and verified it using a commercial extensible processor. Experiments with several benchmarks indicate that our methodology can effectively tackle large programs. It resulted in the synthesis of high-quality custom processors that demonstrated an average speedup of 2.61X and a maximum speedup of 6.32X. The CPU times required for custom processor synthesis were quite small, indicating that the proposed techniques can be applied to embedded software programs of significant complexity.

关键词： Application specific processors Design methodology Embedded software Instruction sets system-on-a-chip Computer architecture Application software Scalability hardware Optimization methods

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