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hardware/software partitioning of software binaries 02

Hardware/software partitioning of software binaries

引用

international conference on Computer-Aided Design

作者： Stitt, G Vahid, F Univ Calif Riverside Dept Comp Sci & Engn Riverside CA 92521 USA

ISBN: (纸本)0780376072

Partitioning an embedded system application among a microprocessor and custom hardware has been shown to improve the performance, power or energy of numerous examples. The advent of single-chip microprocessor/FPGA platforms makes such partitioning even more attractive. Previous partitioning approaches have partitioned sequential program source code, such as C or C++. We introduce a new approach that partitions at the software binary level. Although source code partitioning is preferable from a purely technical viewpoint, binary-level partitioning provides several very practical benefits for commercial acceptance. We demonstrate that binary-level partitioning yields competitive speedup results compared to source-level partitioning, achieving an average speedup of 1.4 compared to 1.5 for eight benchmarks partitioned on a single-chip microprocessor/FPGA device.

关键词： hardware/software partitioning synthesis binary translation decompilation low power assembly language FPGA codesign synthesis

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Proceedings of the Tenth international Symposium on hardware/software codesign: CODES 2002

Proceedings of the Tenth International Symposium on Hardware...

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Proceedings of the Tenth international Symposium on hardware/software codesign: CODES 2002

The proceedings contains 36 papers. Topics discussed include advances in system identification and system design framework, system design methods, design space exploration and architectural design , co-design architecture and synthesis, system partitioning and timing analysis, energy efficiency in system design and scheduling in systems design.

关键词： systems analysis

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Symbolic pointer analysis 02

Symbolic pointer analysis

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international conference on Computer-Aided Design

作者： Zhu, JW Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

ISBN: (纸本)0780376072

One of the bottlenecks in the recent movement of hardware synthesis from behavioral C programs is the difficulty in reasoning about runtime pointer values at compile time. The pointer analysis problem has been investigated in the compiler community for two decades, which has yielded efficient, polynomial time algorithms for context-insensitive analysis. However, at the accuracy level for which hardware synthesis is desired, namely context and flow sensitive analysis, the time and space complexity of the best algorithms reported grow exponentially with program size. In this paper, we present our first step towards a new analysis technology which potentially leads to almost-linear time complexity and sub-linear space complexity algorithm even for the most accurate analysis. The key idea that contributes to this efficiency is to implicitly encode the pointer-to relation in the Boolean domain, thereby capturing the procedure transfer function completely, compactly and canonically. This represents a wide departure from the traditional techniques, all of which explicitly capture pointer-to relation using variations of point-to graph, which have to be re-evaluated for different calling contexts. Experiments for our first flow-insensitive algorithm on common benchmarks show promising result.

关键词： hardware-software codesign integrated circuit design circuit CAD computational complexity Boolean functions program compilers symbolic pointer analysis hardware synthesis behavioral C programs runtime pointer values compile time polynomial time algorithms context-insensitive analysis context sensitive analysis flow sensitive analysis almost-linear time complexity sub-linear space complexity algorithm Boolean domain pointer-to relation encoding procedure transfer function point-to graph variations calling contexts flow-insensitive algorithm

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Extended quasi-static scheduling for formal synthesis and code generation of embedded software 02

Extended quasi-static scheduling for formal synthesis and co...

引用

Proceedings of the Tenth international Symposium on hardware/software codesign: CODES 2002

作者： Su, Feng-Shi Hsiung, Pao-Ann Dept. of Comp. Sci. and Info. Eng. National Chung Cheng University Chiayi-621 Taiwan

ISBN: (纸本)1581135424

With the computerization of most daily-life amenities such as home appliances, the software in a real-time embedded system now accounts for as much as 70% of a system design. On one hand, this increase in software has made embedded systems more accessible and easy to use, while on the other hand, it has also necessitated further research on how complex embedded software can be designed automatically and correctly. Enhancing recent advances in this research, we propose an Extended Quasi-Static Scheduling (EQSS) method for formally synthesizing and automatically generating code for embedded software, using the Complex-Choice Petri Nets (CCPN) model. Our method improves on previous work in three ways: (1) by removing model restrictions to cover a much wider range of applications, (2) by proposing an extended algorithm to schedule the more unrestricted model, and (3) by implementing a code generator that can produce multi-threaded embedded software programs. The requirements of an embedded software are specified by a set of CCPN, which is scheduled using EQSS such that the schedules satisfy limited embedded memory requirements and task precedence constraints. Finally, a POSIX-based multi-threaded embedded software program is generated in the C programming language. Through an example, we illustrate the feasibility and advantages of the proposed EQSS method.

关键词： Embedded systems

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A hierarchical CDFG as intermediate representation for hardware/software codesign 1

A hierarchical CDFG as intermediate representation for hardw...

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international conference on Communications, Circuits and systems

作者： Wu, Q Wang, YF Bian, JN Wu, WM Xue, HX Tsinghua Univ Dept Comp Sci & Technol Beijing 100084 Peoples R China

ISBN: (纸本)0780375475

A hierarchical CDFG model designed as an intermediate representation for hardware/software (HW/SW) codesign is presented in this paper. A new concept of transport node, which represents the communication resources of the system, is proposed in this model. Hierarchical feature can be straightly obtained through extending the definition of nodes, allowing them to nest sub-CDFG recursively. Then it is demonstrated how to build basic control constructs of branches and loops. Explaining in a short introduction to the translation process, such a hierarchical CDFG is suitable for HW/SW codesign as an intermediate representation. The hierarchical CDFG model can capture the design information from source file specified by VHDL or C language. It maintains relative simplicity while providing helpful features for HW/SW partitioning and High-level synthesis tools.

关键词： CDFG (control data flow graph) HW/SW co-design HW/SW partitioning

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Improving embedded system design by means of HW-SW compilation on reconfigurable coprocessors

Improving embedded system design by means of HW-SW compilati...

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15th international Symposium on system synthesis

作者： Moya, José M. Moya, Francisco Rincón, Fernando López, Juan Carlos Dept. of Electronic Engineering Technical University of Madrid Madrid Spain Dept. of Computer Science U. of Castilla-La Mancha Ciudad Real Spain

This article describes a new approach to HW-SW codesign for complex embedded systems, using high-level programming languages. Unlike in previous approaches, the designer does not need to acquire new skills, because most of the design process is automated. The hardware extensions are implemented as simple coprocessors consisting of a reconfigurable datapath and a control memory. Our approach is demonstrated with a simple image processing application, obtaining a 100% performance improvement.

关键词： software engineering

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hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfligurable FPGAs 7

Hardware-software co-synthesis of low power real-time distri...

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7th Asia and South Pacific Design Automation conference/15th international conference on VLSI Design

作者： Shang, L Jha, NK Princeton Univ Dept EE Princeton NJ 08544 USA

ISBN: (纸本)0769514413

In this paper, we present a multi-objective hardware-software co-synthesis system for multi-rate, real-time, low power distributed embedded systems consisting of dynamically reconfigurable FPGAs, processors, and other system resources. We use an evolutionary algorithm based framework for automatically determining the quantity and type of different system resources, and then assigning tasks to different processing elements (PEs) and task communications to communication links. For FPGAs, we propose a two-dimensional, multi-rate cyclic scheduling algorithm, which determines task priorities based on real-time constraints and reconfiguration overhead information, and then schedules tasks based on the resource utilization and reconfiguration condition in both space and time. The FPGA scheduler is integrated in a list-based system scheduler. To the best of our knowledge, this is the first multi-objective co-synthesis system, which uses dynamically, reconfigurable devices to synthesize a distributed embedded system, to target simultaneous optimization of system price and power. Experimental results indicate that our method can reduce schedule length by an average of 41.0% and reconfiguration power by an average of 46.0% compared to the previous method. It also yields multiple system architectures which trade off system price and power under real-time constraints.

关键词： Field programmable gate arrays (FPGA)

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Towards automatic synthesis of a class of application-specific sensor networks

Towards automatic synthesis of a class of application-specif...

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2002 international conference on Compilers, Architecture, and synthesis for Embedded systems, CASES '02

作者： Bakshi, Amol Ou, Jingzhao Prasanna, Viktor K. Dept. of EE-Systems University of Southern California Los Angeles CA 90089 United States

ISBN: (纸本)1581135750

Automatic synthesis of sensor network-based systems can be described as the process of translating a formal specification of application functionality into a particular task mapping, settings of available hardware knobs, and communication and coordination mechanisms among the sensor nodes, so as to meet the performance requirements and constraints. We propose a general methodology to tackle a specific class of this problem, based on analytical performance modeling, multigranularity system simulation, and automatic refinement of model parameters. To demonstrate the utility and feasibility of our proposed methodology, we define a system model for a class of sensor networks, and implement a software framework for its modeling and simulation. Our graphical design environment supports plug-and-play integration of different performance models, simulation and visualization suites, and even automatic design space exploration and optimization tools. Copyright 2002 acm.

关键词： Energy efficiency

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HW/SW partitioning approach for reconfigurable system design

HW/SW partitioning approach for reconfigurable system design

引用

2002 international conference on Compilers, Architecture, and synthesis for Embedded systems, CASES '02

作者： Chehida, K. Ben Auguin, M. I3S University of Nice Sophia Antipolis CNRS Les Algorithmes/Euclide B 2000 route des Lucioles 06903 Sophia-Antipolis Cedex France

ISBN: (纸本)1581135750

This paper presents a Genetic Algorithm (GA) based approach for hardware/software partitioning targeting an architecture composed of a processor and a dynamically reconfigurable datapath (FPGA). From an acyclic task graph and a set of Area-Time implementation trade off points for each task, our GA performs HW/SW partitioning and scheduling such that the global application execution time is minimized. The efficiency of our GA is established through its application to an AC-3 decoder function and its performance is compared with a greedy algorithm. Copyright 2000 acm.

关键词： Genetic algorithms

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An evolutionary scheme for cosynthesis of real-time systems 7

An evolutionary scheme for cosynthesis of real-time systems

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7th Asia and South Pacific Design Automation conference/15th international conference on VLSI Design

作者： Chakraverty, S Ravikumar, CP Choudhuri, DR Netaji Subhas Inst Technol New Delhi 110045 India

ISBN: (纸本)0769514413

We consider the problem of hardware-software cosynthesis of application-specific embedded realtime systems. We assume that these systems are based on a heterogeneous multiprocessor architecture. One of the key problems in the synthesis of such systems is that of scheduling the real-time tasks. Conventional approach to the problem has been to use a task graph to describe the dependencies among tasks and to assign constant weights to the nodes and edges of the graph. ne node weights represent task execution times and the edge weights represent communication times. However, in many real-time applications, the execution time and communication times cannot be determined a-priori. One can use the conventional task graph model in such situations by taking the worst-case times, but such an approach will necessarily be pessimistic and wasteful in terms of resource utilization. We propose a model which treats the task execution times and communication times as stochastic variables with Beta distributions. A stochastic task scheduling algorithm is presented which maximizes the probability of meeting all real-time constraints. A genetic algorithm, which employs the stochastic scheduling algorithm, is used for the synthesis of a high performance embedded system at a minimum cost. We present experimental results for three task graphs.

关键词： embedded real-time systems hardware software cosynthesis hierarhical genetic algorithm multiprocessor architecture stochastic task scheduling task allocation

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