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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

共 1035 条记录，以下是951-960 订阅

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A methodology for the design of application specific instruction set processors (ASIP) using the machine description language LISA 01

A methodology for the design of application specific instruc...

引用

IEEE international conference on Computer-Aided Design

作者： A. Hoffmann O. Schliebusch A. Nohl G. Braun O. Wahlen H. Meyr Integrated Signal Processing Systems RWTH Aachen Germany

ISBN: (纸本)9780780372498

The development of application specific instruction set processors (ASIP) is currently the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that building such an architecture is a difficult task that requires expert knowledge in different domains: application software development tools, processor hardware implementation, and system integration and verification. This paper presents a retargetable framework for ASIP design which is based on machine descriptions in the LISA language. From that, software development tools can be automatically generated including HLL C-compiler, assembler, linker, simulator and debugger frontend. Moreover, synthesizable HDL code can be derived which can then be processed by standard synthesis tools. Implementation results for a low-power ASIP for DVB-T acquisition and tracking algorithms designed with the presented methodology are given.

关键词： Design methodology Application software Application specific processors Buildings Computer architecture Programming Assembly hardware design languages Code standards Digital video broadcasting

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Run-time HW/SW codesign for discrete event systems using dynamically reconfigurable architectures 13

Run-time HW/SW codesign for discrete event systems using dyn...

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13th international Symposium on system synthesis (ISSS 2000)

作者： Noguera, J Badia, RM Univ Autonoma Barcelona E-08193 Barcelona Spain

ISBN: (纸本)0769507654;0769507662

HW/SW codesign and Reconfigurable Computing are commonly used methodologies for digital systems design. However, no previous work has been carried out in order to define a run-rime HW/SW codesign methodology for dynamically reconfigurable architectures. Besides, all previous approaches to reconfigurable computing context scheduling are based on static scheduling techniques. In this paper we present a run-time HW/SW codesign methodology for discrete evens systems using dynamically reconfigurable architectures and a dynamic approach to reconfigurable computing multi-context scheduling. We have applied our methodology to software acceleration, and present the obtained results.

关键词： Acceleration Discrete event systems Dynamic scheduling Embedded system hardware Partitioning algorithms Processor scheduling Reconfigurable architectures Runtime Throughput

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SDL as a system level specification language for application-specific hardware in a rapid prototyping environment 13

SDL as a system level specification language for application...

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13th international Symposium on system synthesis (ISSS 2000)

作者： Muth, A Färber, G Tech Univ Munich Inst Real Time Comp Syst D-8000 Munich Germany

ISBN: (纸本)0769507662

The specification of an embedded system at system level together with co-joint hardware/software synthesis is a goal of many rapid prototyping projects. SDL has been proposed as a formal and abstract specification language will suited for this purpose. The implementation of SDL's asynchronous communication model in application specific hardware, however, is un-proportionally expensive in terms of area and response time. This paper discusses the efficiency of the server model - the implementation model used in all known codesign approaches based on SDL - and compares it with an alternative implementation model for SDL known from software, the activity thread model. In a known from software, the activity thread model. In a combination of both implementation stategies, the communication and synchronization overhead for each application can be minimized, and an efficient implementation on distributed architectures realized. The integration in an existing rapid prototyping design process ins presented as well as results gained from application examples.

关键词： Application software Asynchronous communication Computer architecture Delay Embedded software Embedded system hardware software prototyping Specification languages Yarn

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Specification and synthesis of real-time embedded distributed and parallel multiprocessor-based signal processing systems

Specification and synthesis of real-time embedded distribute...

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Proceedings of the international conference on Compilers, Architecture, and synthesis for Embedded systems (CASES 2000)

作者： Janka, Randall S. Wills, Linda M. Cadence Design Systems Inc. 1117 Perimeter Center West Atlanta GA 30338 United States Sch. of Elec./Computer Engineering Georgia Institute of Technology Atlanta GA 30332-0250 United States

ISBN: (纸本)1581133383

The codesign of embedded real-time signal processing systems is complex. In certain application domains requiring high computational throughput, this complexity is due to the need to employing parallel processing and perhaps using heterogeneous processors. The use of commercial-off-the-shelf (COTS) multiprocessor (MP) hardware and software can reduce codesign complexity. Further complexity reduction can be obtained with emerging synthesis frameworks, which can generate deployable code by leveraging vendor communication and computation libraries. However, these synthesis frameworks are inadequate in providing a sound specification and design methodology (SDM) because they require the designer to first choose the implementation target before specification and design exploration. We have developed a new SDM known as MAGIC that allows the designer to capture the specification in an executable model that can then be used in design exploration to find the optimal COTS MP technology and architecture before committing to that technology. The MAGIC SDM exploits emerging open-standards based VSIPL computation middleware and MPI communication middleware to provide connectivity between specification and design with synthesis frameworks for implementation. This SDM is also shown to be applicable to the system-on-chip (SOC) domain, especially as embodied in a new framework called Virtual Component Co-design from Cadence Design systems.

关键词： Signal processing

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A flexible specification framework for hardware-software codesign 00

A flexible specification framework for hardware-software cod...

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Design, Automation and Test in Europe conference and Exhibition

作者： Jose Manuel Moya Santiago Dominguez Francisco Moya Juan Carlos Lopez Universidad de Castilla-La Mancha Departamento de Informática ESI. P° Universidad 4 13071 Ciudad Read Spain

ISBN: (纸本)0769505376

In this poster, we present a new specification technique for complex hardware-software systems, based on standard high-level programming languages, such as C, C++, Java, Scheme, or Ada, without extensions or semantic changes. Unlike previous approaches, the designer may choose the model of computation and the specification language that best suits her needs, while still being able to formally verify the correctness of the specification. The details of the available hardware and software resources, and the implementation of the different models of computation are encapsulated in libraries to maximize reuse in system specifications.

关键词： hardware/software co-design MODEL CALCULATION Specifications system specifications ADA (PROGRAMMING LANGUAGE) specification description language Posters Designers high-level programming languages accuracy class Libraries reuse

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Coevolvable hardware platform for automatic hardware design of neural networks

Coevolvable hardware platform for automatic hardware design ...

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IEEE international conference on Industrial Technology (ICIT)

作者： O. Hammami K. Kuroda Q. Zhao K. Saito Department of Hardware University of Aizu Fukushima Japan

This paper proposes a system for the automatic hardware design of neural networks based on cooperative coevolutionary paradigms and multiple reconfigurable devices. The authors' system is composed of a logic synthesis tool, multiple reconfigurable devices and an embedded processor executing the coevolutionary algorithm. The partitioning of the engineering design process follows current practices in hardware/software codesign based on both information on arrival rate /spl lambda/ of requests and the service time /spl mu/ of the reconfigurable devices. The system is suitable under some conditions for industrial applications such as a reactive system but also because it can be connected to multiple systems in a totally networked industrial environment which allows download of the same hardware configuration on multiple on ine devices.

关键词： Neural network hardware Neural networks hardware design languages Genetic programming Network synthesis Algorithm design and analysis Approximation algorithms Logic devices Reconfigurable logic Partitioning algorithms

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HW/SW codesign of an engine management system 00

HW/SW codesign of an engine management system

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Design, Automation and Test in Europe conference and Exhibition

作者： M. Baleani A. Ferrari A. Sangiovanni-Vincentelli C. Turchetti Department of EECS University of California Berkeley CA USA Department of Electronics University of Ancona Ancona Italy PARADES E.E.I.G. Rome Italy

ISBN: (纸本)9781581132441

The design process for an engine management system is presented. The functional specification of the system has been captured using C and C++ as specification languages. The validation of the specification has been carried out using functional simulation. Then an architecture for the implementation of the functional specification is selected among a set of three possible alternatives, all based on the same micro-controller; characterized by different hardware-software trade-offs. The choice is motivated by a fast performance estimation that can also be used to identify the parts of the design that could be moved across the hardware-software partition to obtain better cost or better performance. The case study has been performed in the Felix VCC framework.

关键词： Engines Costs Embedded system Design methodology hardware Libraries Performance analysis Digital signal processing Process design Specification languages

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system design based on single language and single-chip Java ASIP microcontroller 00

System design based on single language and single-chip Java ...

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Design, Automation and Test in Europe conference and Exhibition

作者： Sergio Akira Ito Luigi Carro Ricardo Pezzuol Jacobi Inst.of Computer Science UFRGS Brazil Electrical Engineering UFRGS Brazil Dept.of Computer Science UnB Brazil

ISBN: (纸本)0769505376

Microcontrollers have been playing an important role in the embedded market. However, the designer of microcontroller based systems must deal with different languages and tools in the hardware and software development, despite of their distinct design process. This paper presents a new design strategy to implement embedded applications described uniquely in Java, while maintaining software compatibility throughout the design process. Moreover, the target hardware is a single chip FPGA, taking benefit from their low cost and easy reconfiguration to customize the microcontroller. This papers presents the environment and some results of system synthesis.

关键词： Microcontrollers design process Java Java programming language software compatibility embedded application Computer hardware ASIP gene Language updated design software design computer software system design

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system synthesis for multiprocessor embedded applications 00

System synthesis for multiprocessor embedded applications

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Design, Automation and Test in Europe conference and Exhibition

作者： Luigi Carro Marcio Kreutz Flavio R. Wagner Marcio Oyamada DELET UFRGS Av. Osvaldo Aranha 103 90035-190 Porto Alegre RS Brazil PPGC UFRGS Bento Gonçalves 9500 Bloco IV CP 15064 91501-970 Porto Alegre RS Brazil

ISBN: (纸本)0769505376

This paper presents the system synthesis techniques available in S{sup}2E{sup}2S, a CAD environment for the specification, simulation, and synthesis of embedded electronic systems that can be modeled as a combination of analog parts, digital hardware, and software. S{sup}2E{sup}2S is based on a distributed, object-oriented system model, where objects are initially modeled by their behavior and may be later refined into digital or analog hardware and software. system synthesis is targeted to a multiprocessor platform. Each processor, either a custom-designed one or an off-the-shelf component, can have a specialized behavior, like signal processing or control processing. The environment selects processors that best match the desired application by analyzing and comparing processor and application characteristics. The paper illustrates the architecture selection process with concrete examples.

关键词： synthesis Multiprocessor Electronic systems embedded application PROCESSOR signal processing EASE OF APPLICATION Computer hardware

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From high-level specifications down to software implementations of parallel embedded real-time systems 00

From high-level specifications down to software implementati...

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Design, Automation and Test in Europe conference and Exhibition

作者： C. Rust F. Stappert P. Altenbernd J. Tacken C-LAB Fürstenallee 11 33094 Paderborn Germany

ISBN: (纸本)0769505376

In this paper we describe a methodology and accompanied tool support for the development of parallel and distributed embedded real-time system software. The presented approach comprises the complete design flow from the modeling of a distributed controller system by means of a high-level graphical language down to the synthesis of executable code for a given target hardware, whereby the implementation is verified to meet hard real-time constraints. The methodology is mainly based upon the tools SEA (system Engineering and Animation) and CHaRy (The C-LAB Hard Real-Time system).

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