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检索条件"任意字段=ACM International Conference on Hardware/software - Codesign and System Synthesis"

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Communication synthesis and HW/SW integration for embedded system design

Communication synthesis and HW/SW integration for embedded s...

引用

6th international Workshop on hardware/software codesign (CODES/CASHE 98)

作者： Gogniat, G Auguin, M Bianco, L Pegatoquet, A Univ Nice CNRS F-06041 Nice France

ISBN: (纸本)0818684429

The implementation of codesign applications generally requires the use of heterogeneous resources (e.g., processor cores, hard,rare accelerators) in one system. Interfacing hardware and software components together and providing communications bent een them are particularly, error proned and time consuming tasks. Hence, on the basis of a generic architecture we propose an extended communication synthesis method that provides characterization of communications and their implementation scheme in the target architecture. This method takes place after partitioning and scheduling and can constitute the basis of a back end of a codesign framework leading to HW/SW integration.

关键词： Computer architecture

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Communication and interface synthesis on a rapid prototyping hardware/software codesign system 11

Communication and interface synthesis on a rapid prototyping...

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11th international Symposium on system synthesis (ISSS 98)

作者： Hwang, YT Wang, YH Natl Yunlin Univ Sci & Technol Dept Elect Engn Touliu 64045 Yunlin Taiwan

ISBN: (纸本)0818686235

In this paper, rye propose the target board architecture of a rapid prototyping embedded system based on hardware software codesign. The target board contains a TMS320C30 DSP processor and up to four Xilinx XC4025E FPGAs. Various communication channels between the C30 and the FPGAs are provided and a master-master computing paradigm is supported. HW/SW communication protocols, ranging from handshaking, batch to queue controlled, as well as the corresponding interfaces are described in VHDL and C codes respectively and can be easily augmented to the mapped design. A codesign implementation example based on G.728 LD-CELP speech decoder shows the proposed communication protocols and interfaces lead to very small rime and circuitry overhead.

关键词： hardware-software codesign

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Towards interprocess communication and interface synthesis for a heterogenous real-time rapid prototyping environment

Towards interprocess communication and interface synthesis f...

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6th international Workshop on hardware/software codesign (CODES/CASHE 98)

作者： Fischer, F Muth, A Farber, G Tech Univ Munich Lab Process Control & Real Time Syst D-8000 Munchen Germany

ISBN: (纸本)0818684429

Rapid Prototyping has been proposed as a means to reduce development time and costs of real-rime systems. Our approach uses a heterogeneous, tightly coupled multiprocessor system based on off-the-shelf components as target architecture for an executable prototype, which is generated from the specification in an automated design process. Here, too, we aim to use existing tools and languages. But interface and communication synthesis, while being the key requirement of an automated translation of a abstract specification to a distributed system, is not yet state-of-the-art. The sensitivity of the overall performance of multiprocessor systems to overhead and latency introduced by communication on the other hand calls for an efficient interprocess communication (IPC). This paper presents concept and implementation of IPC functions which, implementing the message queue semantics of the specification language SDL, links the standard components of our multiprocessor system in an efficient manner, while at the same time providing the interface synthesis needed by the automated generation of a rapid prototype. The experiences gained when implementing a non-trivial, real-world CAN controller and monitor application on our rapid prototyping environment, are described as a first proof of concept.

关键词： communication synthesis rapid prototyping SDL hard real-time task classification model

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Integrating communication protocol selection with partitioning in hardware/software codesign 11

Integrating communication protocol selection with partitioni...

引用

11th international Symposium on system synthesis (ISSS 98)

作者： Knudsen, PV Madsen, J Tech Univ Denmark Dept Informat Technol Lyngby Denmark

ISBN: (纸本)0818686235

This paper presents a codesign approach which incorporates communication protocol selection as a design parameter within hardware/software partitioning The presented approach takes into account data transfer rates depending on communication protocol types and configurations and different operating frequencies of system components, i.e. CPUs, ASICs, and busses. It also takes into account the timing and area influences of drivers and driller calls needed to perform the communication. The approach is illustrated by a number of design space exploration experiments which use models of the PCI and USE communication protocols.

关键词： Data transfer

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Interface synthesis for embedded applications in a codesign environment

Interface synthesis for embedded applications in a codesign ...

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Proceedings of the 1998 11th international conference on VLSI Design

作者： Basu, Anupam Mitra, R.S. Marwedel, P. I.I.T. Kharagpur Kharagpur India

In embedded systems, programmable peripherals are often coupled with the main programmable processor to achieve the desired functionality. Interfacing such peripherals with the processor qualifies as an important task of hardware software codesign. In this paper, three important aspects of such interfacing, namely, the allocation of addresses to the devices, allocation of device drivers, and approaches to handle events and transitions have been discussed. The proposed approaches have been incorporated in a codesign system MICKEY. The paper includes a number of examples, taken from results synthesized by MICKEY, to illustrate the ideas.

关键词： Interfaces (computer)

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hardware/software co-synthesis with memory hierarchies 98

Hardware/software co-synthesis with memory hierarchies

引用

IEEE/acm international conference on Computer-Aided Design

作者： Li, YB Wolf, W Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)1581130082

This paper introduces the first hardware/software cosynthesis algorithm of distributed real-time systems that optimizes memory hierarchy along with the rest of the architecture. Our algorithm synthesize a set of real-time tasks with data dependencies onto a heterogeneous multiprocessor architecture that meets the performance constraints with minimized cost. Our algorithm chooses cache sizes and allocates tasks to caches as part of co-synthesis. Experimental results, including examples from the literature and results on an MPEG-2 encoder, show that our algorithm is efficient and compared with existing algorithms, it can reduce the overall cost of the synthesized system.

关键词： Computer aided network analysis

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Real time collision detection and avoidance: A case study for design space exploration in HW-SW codesign

Real time collision detection and avoidance: A case study fo...

引用

Proceedings of the 1998 11th international conference on VLSI Design

作者： Lodha, Sandeep K. Gupta, Shashank Banerjee, Subhashis Balakrishnan, M. Indian Inst of Technology New Delhi India

In this paper we study a collision detection algorithm and partition it into hardware and software parts to enhance the performance of the system and achieve the real time goal (25 frames/sec). We explore the design space to identify various feasible implementations on software, hardware, firmware and mixed platforms. The platforms considered are the Intel's processors and Sun ULTRA1 for software, MOTOROLA DSP56002 for firmware XILINX FPGAs for hardware. The mixed implementations include combinations of the above. A number of implementations discussed establish that factors such as time constraint, pin count and interface requirements strongly influence the design options.

关键词： Computer architecture

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CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems

CORDS: Hardware-software co-synthesis of reconfigurable real...

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Proceedings of the 1998 IEEE/acm international conference on Computer-Aided Design, ICCAD

作者： Dick, Robert P. Jha, Niraj K. Princeton Univ Princeton United States

Field programmable gate arrays (FPGAs) are commonly used in embedded systems. Although it is possible to reconfigure some FPGAs while an embedded system is operational, this feature is seldom exploited. Recent improvements in the flexibility and reconfiguration speed of FPGAs have made it practical to reconfigure them dynamically, reducing the amount of hardware required in an embedded system. We have developed a system, called CORDS, which synthesizes multi-rate, real-time, periodic distributed embedded systems containing dynamically reconfigurable FPGAs. Executing different tasks on the same FPGA requires that potentially time-consuming reconfiguration be carried out between tasks. CORDS uses a novel preemptive, dynamic priority, multi-rate scheduling algorithm to deal with this problem. To the best of our knowledge, dynamically reconfigured FPGAs have not previously been used in hardware-software co-synthesis of embedded systems. Experimental results indicate that using dynamically reconfigured FPGAs in distributed real-time embedded systems has the potential to reduce their price and allow the synthesis of architectures which meet system specifications that would otherwise be infeasible.

关键词： Embedded systems

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Interface synthesis: A vertical slice from digital logic to software components

Interface synthesis: A vertical slice from digital logic to ...

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Proceedings of the 1998 IEEE/acm international conference on Computer-Aided Design, ICCAD

作者： Borriello, Gaetano Lavagno, Luciano Ortega, Ross B. Univ of Washington Seattle WA United States

Interface synthesis seeks to automate the process of interconnecting components. There are many levels of interconnection that must be considered including electrical, power, logic, register-transfer, device drivers, and higher software levels. This presentation will cover a vertical slice of the interfacing problem from digital logic up to coordinating communications between software components. The focus will be within an embedded systems context where the interfacing is between processors and memory and peripheral blocks as is the case in system-on-a-chip design. The structure of the tutorial will parallel the history of CAD efforts in this area. We will begin with the early work in interface specification and logic synthesis then proceed on to the problems of interconnecting hardware to processors and their software, and finish with purely software interfaces involving inter-process communication and protocols between multiple processors. At each level we will discuss specification, synthesis, and verification aspects as well as highlight the currently available tools and on-going research efforts.

关键词： Interfaces (computer)

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COHRA: hardware-software co-synthesis of hierarchical distributed embedded system architectures

COHRA: Hardware-software co-synthesis of hierarchical distri...

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Proceedings of the 1998 11th international conference on VLSI Design

作者： Dave, Bharat P. Jha, Niraj K. Princeton Univ Princeton United States

hardware-software co-synthesis of an embedded system architecture entails partitioning of its specification into hardware and software modules suck that its real-time and other constraints are met. Embedded systems are generally specified in terms of a set of acyclic task graphs. For medium-to-large scale embedded systems, the task graphs are usually hierarchical in nature. The embedded system architecture, which is the output of the co-synthesis system, may itself be non-hierarchical or hierarchical. Traditional non-hierarchical architectures create communication and processing bottlenecks, and are impractical for large embedded systems. Such systems require a large number of processing elements and communication links connected in a hierarchical manner, thus forming a hierarchical distributed architecture, to meet performance and cost objectives. In this paper, we address the problem of hardware-software co-synthesis of hierarchical distributed embedded system architectures from hierarchical or non-hierarchical task graphs. Our co-synthesis algorithm has the following features: 1) it supports periodic task graphs with real-time constraints, 2) it supports pipelining of task graphs, 3) it supports a heterogeneous set of PEs and communication links, 4) it allows both sequential and concurrent modes of communication and computation, 5) it employs a combination of preemptive and non-preemptive static scheduling, 6) it employs a new task clustering technique suitable for hierarchical task graphs, and 7) it uses the concept of association arrays to tackle the problem of multi-rate tasks encountered in multimedia systems. We show how our co-synthesis algorithm can be easily extended to consider fault tolerance or low power objectives or both. Although hierarchical architectures have been proposed before, to the best of our knowledge, this is the first time the notion of hierarchical task graphs and hierarchical architectures has been supported in a co-synthesis algorithm

关键词： Computer architecture

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