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A cost-driven compilation framework for speculative parallelization of sequential programs

A cost-driven compilation framework for speculative parallel...

引用

conference on programming language design and implementation

作者： Du, ZH Lim, CC Li, XF Yang, C Zhao, QY Ngai, TF Intel China Ltd Res Ctr Beijing Peoples R China Intel Corp Programming Syst Lab Santa Clara CA USA

The emerging hardware support for thread-level speculation opens new opportunities to parallelize sequential programs beyond the traditional limits. By speculating that many data dependences are unlikely during runtime, consecutive iterations of a sequential loop can be executed speculatively in parallel. Runtime parallelism is obtained when the speculation is correct. To take full advantage of this new execution model, a program needs to be programmed or compiled in such a way that it exhibits high degree of speculative thread-level parallelism. We propose a comprehensive cost-driven compilation framework to perform speculative parallelization. Based on a misspeculation cost model, the compiler aggressively transforms loops into optimal speculative parallel loops and selects only those loops whose speculative parallel execution is likely to improve program performance. The framework also supports and uses enabling techniques such as loop unrolling, software value prediction and dependence profiling to expose more speculative parallelism. The proposed framework was implemented on the ORC compiler. Our evaluation showed that the cost-driven speculative parallelization was effective. Our compiler was able to generate good speculative parallel loops in ten Spec2000Int benchmarks, which currently achieve an average 8% speedup. We anticipate an average 15.6% speedup when all enabling techniques are in place.

关键词： languages design algorithms performance speculative multithreading speculative parallel threading thread-level speculation speculative parallelization cost-driven compilation loop transformation

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Spatial computation

Spatial computation

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11th International conference on Architectural Support for programming languages and Operating Systems

作者： Budiu, M Venkataramani, G Chelcea, T Goldstein, SC Carnegie Mellon Univ Pittsburgh PA 15213 USA

This paper describes a computer architecture, Spatial Computation (SC), which is based on the translation of high-level language programs directly into hardware structures. SC program implementations are completely distributed, with no centralized control. SC circuits are optimized for wires at the expense of computation units. In this paper we investigate a particular implementation of SC: ASH (Application-Specific Hardware). Under the assumption that computation is cheaper than communication, ASH replicates computation units to simplify interconnect, building a system which uses very simple, completely dedicated communication channels. As a consequence, communication on the datapath never requires arbitration;the only arbitration required is for accessing memory. ASH relies on very simple hardware primitives, using no associative structures, no multiported register files, no scheduling logic, no broadcast, and no clocks. As a consequence, ASH hardware is fast and extremely power efficient. In this work we demonstrate three features of ASH: (1) that such architectures can be built by automatic compilation of C programs;(2) that distributed computation is in some respects fundamentally different from monolithic superscalar processors;and (3) that ASIC implementations of ASH use three orders of magnitude less energy compared to high-end superscalar processors, while being on average only 33% slower in performance (3.5x worst-case).

关键词： measurement performance design spatial computation dataflow machine application-specific hardware low-power

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Prefetch injection based on hardware monitoring and object metadata

Prefetch injection based on hardware monitoring and object m...

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conference on programming language design and implementation

作者： Adl-Tabatabai, AR Hudson, RL Serrano, MJ Subramoney, S Intel Corp Microprocessor Technol Lab Programming Syst Lab Santa Clara CA USA

Cache miss stalls hurt performance because of the large gap between memory and processor speeds - for example, the popular server benchmark SPEC JBB2000 spends 45% of its cycles stalled waiting for memory requests on the Itanium(R) 2 processor. Traversing linked data structures causes a large portion of these stalls. Prefetching for linked data structures remains a major challenge because serial data dependencies between elements in a linked data structure preclude the timely materialization of prefetch addresses. This paper presents Mississippi Delta (MS Delta), a novel technique for prefetching linked data structures that closely integrates the hardware performance monitor (HPM), the garbage collector's global view of heap and object layout, the type-level metadata inherent in type-safe programs, and JIT compiler analysis. The garbage collector uses the HPM's data cache miss information to identify cache miss intensive traversal paths through linked data structures, and then discovers regular distances (deltas) between these linked objects. JIT compiler analysis injects prefetch instructions using deltas to materialize prefetch addresses. We have implemented MS Delta in a fully dynamic profile-guided optimization system: the StarJIT dynamic compiler [1] and the ORP Java virtual machine [9]. We demonstrate a 28-29% reduction in stall cycles attributable to the high-latency cache misses targeted by MS Delta and a speedup of 11-14% on the cache miss intensive SPEC JBB2000 benchmark.

关键词： prefetching compiler optimization garbage collection cache misses profile-guided optimization virtual machines

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A practical type system and language for reference immutability

A practical type system and language for reference immutabil...

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19th conference on Object-Oriented programming, Systems, languages, and Applications

作者： Birka, A Ernst, MD MIT Comp Sci & Artificial Intelligence Lab Cambridge MA 02139 USA

This paper describes a type system that is capable of expressing and enforcing immutability constraints. The specific constraint expressed is that the abstract state of the object to which an immutable reference refers cannot be modified using that reference. The abstract state is (part of) the transitively reachable state: that is, the state of the object and all state reachable from it by following references. The type system permits explicitly excluding fields or objects from the abstract state of an object. For a statically type-safe language, the type system guarantees reference immutability. If the language is extended with immutability downcasts, then run-time checks enforce the reference immutability constraints. In order to better understand the usability and efficacy of the type system, we have implemented an extension to Java, called Javari, that includes all the features of our type system. Javari is interoperable with Java and existing JVMs. It can be viewed as a proposal for the semantics of the Java const keyword, though Javari's syntax uses readonly instead. This paper describes the design and implementation of Javari, including the type-checking rules for the language. This paper also discusses experience with 160,000 lines of Javari code. Javari was easy to use and provided a number of benefits, including detecting errors in well-tested code.

关键词： type system verification immutability readonly mutable Javari Java const

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Mirrors: design principles for meta-level facilities of object-oriented programming languages 04

Mirrors: design principles for meta-level facilities of obje...

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Proceedings of the 19th annual acm sigplan conference on Object-oriented programming, systems, languages, and applications

作者： Gilad Bracha David Ungar Sun Microsystems Santa Clara CA Sun Microsystems Mountain View CA

We identify three design principles for reflection and metaprogramming facilities in object oriented programming languages. Encapsulation: meta-level facilities must encapsulate their implementation. Stratification: m... 详细信息

ISBN: (纸本)9781581138313

We identify three design principles for reflection and metaprogramming facilities in object oriented programming languages. Encapsulation: meta-level facilities must encapsulate their implementation. Stratification: meta-level facilities must be separated from base-level functionality. Ontological correspondence: the ontology of meta-level facilities should correspond to the ontology of the language they manipulate. Traditional/mainstream reflective architectures do not follow these precepts. In contrast, reflective APIs built around the concept of mirrors are characterized by adherence to these three principles. Consequently, mirror-based architectures have significant advantages with respect to distribution, deployment and general purpose metaprogramming.

关键词： smalltalk mirrors java metaprogramming reflection self

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Proceedings of the acm sigplan conference on programming language design and implementation (PLDI): Foreword

Proceedings of the ACM SIGPLAN Conference on Programming Lan...

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Proceedings of the acm sigplan 2002 conference on programming language design and implementation (PLDI'02)

作者： Hendren, Laurie

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The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction

The design, implementation, and evaluation of a compiler alg...

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conference on programming language design and implementation

作者： Hsu, CH Kremer, U Rutgers State Univ Dept Comp Sci Piscataway NJ 08855 USA

This paper presents the design and implementation of a compiler algorithm that effectively optimizes programs for energy usage using dynamic voltage scaling (DVS). The algorithm identifies program regions where the CPU can be slowed down with negligible performance loss. It is implemented as a source-to-source level transformation using the SUIF2 compiler infrastructure. Physical measurements on a high-performance laptop show that total system (i.e., laptop) energy savings of up to 28% can be achieved with performance degradation of less than 5% for the SPECfp95 benchmarks. On average, the system energy and energy-delay product are reduced by 11% and 9%, respectively, with a performance slowdown of 2%. It was also discovered that the energy usage of the programs using our DVS algorithm is within 6% from the theoretical lower bound. To the best of our knowledge, this is one of the first work that evaluates DVS algorithms by physical measurements.

关键词： dynamic voltage scaling energy savings

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Proceeding of the acm sigplan 2002 conference on programming language design and implementation® (PLD102)

Proceeding of the ACM SIGPLAN 2002 conference on programming...

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Proceedings of the acm sigplan 2002 conference on programming language design and implementation (PLDI'02)

The proceedings contains 28 papers from the acm sigplan 2002 conference on programming language design and implementation (PLDI'02). Topics discussed include: flow-sensitive type qualifiers;fast copy coalescing and live-range identification;preference-directed graph coloring;a system and language for building system-specific, static analyses and deriving specialized program analyses for certifying component-client conformance.

关键词： Computer programming languages

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Taming the IXP network processor

Taming the IXP network processor

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conference on programming language design and implementation

作者： George, L Blume, M Toyota Technol Inst Chicago Chicago IL USA

We compile Nova, a new language designed for writing network processing applications, using a back end based on integer-linear programming (ILP) for register allocation, optimal bank assignment, and spills. The compiler's optimizer employs CPS as its intermediate representation;some of the invariants that this IR guarantees are essential for the formulation of a practical ILP model. Appel and George used a similar ILP-based technique for the IA32 to decide which variables reside in registers but deferred the actual assignment of colors to a later phase. We demonstrate how to carry over their idea to an architecture with many more banks, register aggregates, variables with multiple simultaneous register assignments, and, very importantly, one where bank- and register-assignment cannot be done in isolation from each other. Our approach performs well in practise-without causing an explosion in size or solve time of the generated integer linear programs.

关键词： network processors Intel IXA integer linear programming register allocation bank assignment programming languages code generation

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The nesC language:: A holistic approach to networked embedded systems 03

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conference on programming language design and implementation

作者： Gay, D Levis, P von Behren, R Welsh, M Brewer, E Culler, D Univ Calif Berkeley EECS Dept Berkeley CA 94720 USA Intel Res Berkeley Berkeley CA 94704 USA

ISBN: (纸本)9781581136623

We present nesC, a programming language for networked embedded systems that represent a new design space for application developers. An example of a networked embedded system is a sensor network, which consists of (potentially) thousands of tiny, low-power "motes," each of which execute concurrent, reactive programs that must operate with severe memory and power constraints. nesC's contribution is to support the special needs of this domain by exposing a programming model that incorporates event-driven execution, a flexible concurrency model, and component-oriented application design. Restrictions on the programming model allow the nesC compiler to perform whole-program analyses, including data-race detection (which improves reliability) and aggressive function inlining (which reduces resource consumption). nesC has been used to implement TinyOS, a small operating system for sensor networks, as well as several significant sensor applications. nesC and TinyOS have been adopted by a large number of sensor network research groups, and our experience and evaluation of the language shows that it is effective at supporting the complex, concurrent programming style demanded by this new class of deeply networked systems.

关键词： programming languages C concurrency data races components modules first-order nesC TinyOS

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