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Shangri-la: Achieving high performance from compiled network applications while enabling ease of programming

acm sigplan NOTICES 2005年第6期40卷 224-236页

作者： Chen, MK Li, XF Lian, RQ Lin, JH Liu, LX Liu, T Ju, R Intel Corp Microproc Technol Labs Santa Clara CA 95051 USA Intel China Res Ctr Ltd Beijing Peoples R China Chinese Acad Sci Inst Comp Technol Beijing Peoples R China

programming network processors is challenging. To sustain high line rates, network processors have extremely tight memory access and instruction budgets. Achieving desired performance has traditionally required hand-coded assembly. Researchers have recently proposed high-level programming languages for packet processing, but the challenges of compiling these languages into code that is competitive with hand-tuned assembly remain unanswered. This paper describes the Shangri-La compiler, which accepts a packet program written in a C-like high-level language and applies scalar and specialized optimizations to generate a highly optimized binary. Hot code paths identified by profiling are mapped across processing elements to maximize processor utilization. Since our compilation target has no hardware caches, software-controlled caches are generated for frequently accessed application data structures. Packet handling optimizations significantly reduce per-packet memory access and instruction counts. Finally, a custom stack model maps stack frames to the fastest levels of the target processor's heterogeneous memory hierarchy. Binaries generated by the compiler were evaluated on the Intel IXP2400 network processor with eight packet processing cores and eight threads per core. Our results show the importance of both traditional and specialized optimization techniques for achieving the maximum forwarding rates on three network applications, L3-Switch, MPLS and Firewall.

关键词： packet processing network processors chip multiprocessors throughput-oriented computing program partitioning dataflow programming

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Enforcing isolation and ordering in STM

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acm sigplan NOTICES 2007年第6期42卷 78-88页

作者： Shpeisman, Tatiana Menon, Vijay Adl-Tabatabai, Ali-Reza Balensiefer, Steven Grossman, Dan Hudson, Richard L. Moore, Katherine F. Saha, Bratin Intel Corp Programming Syst Lab Santa Clara CA 95054 USA Univ Washington Dept Comp Sci & Engn Seattle WA 98195 USA

Transactional memory provides a new concurrency control mechanism that avoids many of the pitfalls of lock-based synchronization. High-performance software transactional memory (STM) implementations thus far provide weak atomicity: Accessing shared data both inside and outside a transaction can result in unexpected, implementation-dependent behavior. To guarantee isolation and consistent ordering in such a system, programmers are expected to enclose all shared-memory accesses inside transactions. A system that provides strong atomicity guarantees isolation even in the presence of threads that access shared data outside transactions. A strongly-atomic system also orders transactions with conflicting non-transactional memory operations in a consistent manner. In this paper, we discuss some surprising pitfalls of weak atomicity, and we present an STM system that avoids these problems via strong atomicity. We demonstrate how to implement non-transactional data accesses via efficient read and write barriers, and we present compiler optimizations that further reduce the overheads of these barriers. We introduce a dynamic escape analysis that differentiates private and public data at runtime to make barriers cheaper and a static not-accessed-in-transaction analysis that removes many barriers completely. Our results on a set of Java programs show that strong atomicity can be implemented efficiently in a high-performance STM system.

关键词： algorithms measurement performance design experimentation languages transactional memory strong atomicity weak atomicity isolation ordering escape analysis compiler optimizations code generation virtual machines

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Reasoning about continuations with control effects

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sigplan Notices (acm Special Interest Group on programming languages) 1989年第7期24卷 218-226页

作者： Jouvelot, Pierre Gifford, David K. Ecole des Mines France

We present a new static analysis method for first-class continuations that uses an effect system to classify the control domain behavior of expressions in a typed polymorphic language. We introduce two new control effects, goto and comefrom, that describe the control flow properties of expressions. An expression that does not have a goto effect is said to be continuation following because it will always call its passed return continuation. An expression that does not have a comefrom effect is said to be continuation discarding because it will never preserve its return continuation for later use. Unobservable control effects can be masked by the effect system. Control effect soundness theorems guarantee that the effects computed statically by the effect system are a conservative approximation of the dynamic behavior of an expression.

关键词： Computer programming languages

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User-changeable visibility: Resolving unanticipated name clashes in traits

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acm sigplan NOTICES 2007年第10期42卷 171-190页

作者： Ducasse, Stephane Wuyts, Roel Bergel, Alexandre INRIA Futurs LISTIC Univ Savoie Language & Software evolut Le Bourget Du Lac France IMEC Louvain Belgium Univ Libre Bruxelles Brussels Belgium LERO Trinity Coll Dublin Ireland

A trait is a unit of behaviour that can be composed with other traits and used by classes. Traits offer an alternative to multiple inheritance. Conflict resolution of traits, while flexible, does not completely handle accidental method name conflicts: if a trait with method m is composed with another trait defining a different method m then resolving the conflict may prove delicate or infeasible in cases where both versions of m are still needed. In this paper we present freezeable traits, which provide an expressive composition mechanism to support unanticipated method composition conflicts. Our solution introduces private trait methods and lets the class composer change method visibility at composition time (from public to private and vice versa). Moreover two class composers may use different composition policies for the same trait, something which is not possible in mainstream languages. This approach respects the two main design principles of traits: the class composer is empowered and traits can be flattened away. We present an implementation of freezable traits in Smalltalk. As a side-effect of this implementation we introduced private (early-bound and invisible) methods to Smalltalk by distinguishing object-sends from self-sends. Our implementation uses compile-time bytecode manipulation and, as such, introduces no run-time penalties.

关键词： languages dynamic typing traits encapsulation information hiding composition

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Merge: A programming model for heterogeneous multi-core systems

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acm sigplan NOTICES 2008年第3期43卷 287-296页

作者： Linderman, Michael D. Collins, Jamison D. Wang, Hong Meng, Teresa H. Stanford Univ Dept Elect Engn Stanford CA 94305 USA Intel Corp Microarchitecture Res Lab Santa Cruz CA USA

In this paper we propose the Merge framework, a general purpose programming model for heterogeneous multi-core systems. The Merge framework replaces current ad hoc approaches to parallel programming on heterogeneous platforms with a rigorous, library-based methodology that can automatically distribute computation across heterogeneous cores to achieve increased energy and performance efficiency. The Merge framework provides (1) a predicate dispatch-based library system for managing and invoking function variants for multiple architectures;(2) a high-level, library-oriented parallel language based on map-reduce;and (3) a compiler and runtime which implement the map-reduce language pattern by dynamically selecting the best available function implementations for a given input and machine configuration. Using a generic sequencer architecture interface for heterogeneous accelerators, the Merge framework can integrate function variants for specialized accelerators, offering the potential for to-the-metal performance for a wide range of heterogeneous architectures, all transparent to the user. The Merge framework has been prototyped on a heterogeneous platform consisting of an Intel Core 2 Duo CPU and an 8-core 32-thread Intel Graphics and Media Accelerator X3000, and a homogeneous 32-way Unisys SNIP system with Intel Xeon processors. We implemented a set of benchmarks using the Merge framework and enhanced the library with X3000 specific implementations, achieving speedups of 3.6x - 8.5x using the X3000 and 5.2x - 22x using the 32-way system relative to the straight C reference implementation on a single IA32 core.

关键词： performance design languages heterogeneous multi-core GPGPU predicate dispatch

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X10: An object-oriented approach to non-uniform cluster computing

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acm sigplan NOTICES 2005年第10期40卷 519-538页

作者： Charles, P Donawa, C Ebcioglu, K Grothoff, C Kielstra, A von Praun, C Saraswat, V Sarkar, V IBM TJ Watson Res Ctr Yorktown Hts NY 10598 USA Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90095 USA IBM Toronto Lab Markham ON L6G 1C7 Canada

It is now well established that the device scaling predicted by Moore's Law is no longer a viable option for increasing the clock frequency of future uniprocessor systems at the rate that had been sustained during the last two decades. As a result, future systems are rapidly moving from uniprocessor to multiprocessor configurations, so as to use parallelism instead of frequency scaling as the foundation for increased compute capacity. The dominant emerging multi processor structure for the future is a Non- Uniform Cluster Computing (NUCC) system with nodes that are built out of multi-core SMP chips with non-uniform memory hierarchies, and interconnected in horizontally scalable cluster configurations such as blade servers. Unlike previous generations of hardware evolution, this shift will have a major impact on existing software. Current 00 language facilities for concurrent and distributed programming are inadequate for addressing the needs of NUCC systems because they do not Support the notions of non-uniform data access within a node, or of tight coupling of distributed nodes. We have designed a modern object-oriented programming language, X10, for high performance, high productivity programming of NUCC systems. A member of the partitioned global address space family of languages, X10 highlights the explicit reification of locality in the form of places;lightweight activities embodied in async, future, foreach, and ateach constructs;a construct for termination detection (finish);the use of lock-free synchronization (atomic blocks);and the manipulation of cluster-wide global data structures. We present an overview of the X10 programming model and language, experience with our reference implementation, and results from some initial productivity comparisons between the X10 and JAVA (TM) languages.

关键词： languages performance design X10 Java multithreading non-uniform cluster computing (NUCC) partitioned global address space (PGAS) places data distribution atomic blocks clocks scalability productivity

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Mul-T: a high-performance parallel Lisp

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sigplan Notices (acm Special Interest Group on programming languages) 1989年第7期24卷 81-90页

作者： Kranz, David Halstead Jr., Robert H. Mohr, Eric MIT United States

Mul-T is a parallel Lisp system, based on Multilisp's future construct, that has been developed to run on an Encore Multimax multiprocessor. Mul-T is an extended version of the Yale T system and uses the T system's ORBIT compiler to achieve 'production quality' performance on stock hardware - about 100 times faster than Multilisp. Mul-T shows that futures can be implemented cheaply enough to be useful in a production-quality system. Mul-T is fully operational, including a user interface that supports managing groups of parallel tasks.

关键词： Computer programming languages

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Static Analysis for Probabilistic Programs: Inferring Whole Program Properties from Finitely Many Paths 13

Static Analysis for Probabilistic Programs: Inferring Whole ...

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acm sigplan conference on programming language design and implementation

作者： Sriram Sankaranarayanan Aleksandar Chakarov Sumit Gulwani University of Colorado Microsoft Research

ISBN: (纸本)9781450320146

We propose an approach for the static analysis of probabilistic programs that sense, manipulate, and control based on uncertain data. Examples include programs used in risk analysis, medical decision making and cyber-physical systems. Correctness properties of such programs take the form of queries that seek the probabilities of assertions over program variables. We present a static analysis approach that provides guaranteed interval bounds on the values (assertion probabilities) of such queries. First, we observe that for probabilistic programs, it is possible to conclude facts about the behavior of the entire program by choosing a finite, adequate set of its paths. We provide strategies for choosing such a set of paths and verifying its adequacy. The queries are evaluated over each path by a combination of symbolic execution and probabilistic volume-bound computations. Each path yields interval bounds that can be summed up with a "coverage" bound to yield an interval that encloses the probability of assertion for the program as a whole. We demonstrate promising results on a suite of benchmarks from many different sources including robotic manipulators and medical decision making programs.

关键词： Probabilistic programming Program Verification Volume Bounding Symbolic Execution Monte-Carlo Sampling

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Input Responsiveness: Using Canary Inputs to Dynamically Steer Approximation

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acm sigplan NOTICES 2016年第6期51卷 161-176页

作者： Laurenzano, Michael A. Hill, Parker Samadi, Mehrzad Mahlke, Scott Mars, Jason Tang, Lingjia Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

This paper introduces Input Responsive Approximation ( IRA), an approach that uses a canary input - a small program input carefully constructed to capture the intrinsic properties of the original input - to automatically control how program approximation is applied on an input-by-input basis. Motivating this approach is the observation that many of the prior techniques focusing on choosing how to approximate arrive at conservative decisions by discounting substantial differences between inputs when applying approximation. The main challenges in overcoming this limitation lie in making the choice of how to approximate both effectively (e.g., the fastest approximation that meets a particular accuracy target) and rapidly for every input. With IRA, each time the approximate program is run, a canary input is constructed and used dynamically to quickly test a spectrum of approximation alternatives. Based on these runtime tests, the approximation that best fits the desired accuracy constraints is selected and applied to the full input to produce an approximate result. We use IRA to select and parameterize mixes of four approximation techniques from the literature for a range of 13 image processing, machine learning, and data mining applications. Our results demonstrate that IRA significantly outperforms prior approaches, delivering an average of 10.2x speedup over exact execution while minimizing accuracy losses in program outputs.

关键词： Performance Runtime Systems Compilers Approximate Computing Performance Experimentation design

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Fault-tolerant typed assembly language

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acm sigplan NOTICES 2007年第6期42卷 42-53页

作者： Perry, Frances Mackey, Lester Reis, George A. Ligatti, Jay August, David I. Walker, David Princeton Univ Dept Comp Sci & Elect Engn Princeton NJ 08544 USA Univ S Florida Dept Comp Sci & Comp Engn Tampa FL 33620 USA

A transient hardware fault occurs when an energetic particle strikes a transistor, causing it to change state. Although transient faults do not permanently damage the hardware, they may corrupt computations by altering stored values and signal transfers. In this paper, we propose a new scheme for provably safe and reliable computing in the presence of transient hardware faults. In our scheme, software computations are replicated to provide redundancy while special instructions compare the independently computed results to detect errors before writing critical data. In stark contrast to any previous efforts in this area, we have analyzed our fault tolerance scheme from a formal, theoretical perspective. To be specific, first, we provide an operational semantics for our assembly language, which includes a precise formal definition of our fault model. Second, we develop an assembly-level type system designed to detect reliability problems in compiled code. Third, we provide a formal specification for program fault tolerance under the given fault model and prove that all well-typed programs are indeed fault tolerant. In addition to the formal analysis, we evaluate our detection scheme and show that it only takes 34% longer to execute than the unreliable version.

关键词： languages reliability theory verification transient hardware faults soft faults fault tolerance type systems typed assembly language

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