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检索条件"任意字段=ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 1988"

共 918 条记录，以下是631-640 订阅

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MaJIC:: Compiling MATLAB for speed and responsiveness 02

MaJIC:: Compiling MATLAB for speed and responsiveness

引用

conference on programming language design and implementation (pldi 02)

作者： Almási, G Padua, D Univ Illinois Dept Comp Sci Champaign IL 60680 USA

ISBN: (纸本)9781581134636

This paper presents and evaluates techniques to improve the execution performance of MATLAB. Previous efforts concentrated on source to source translation and batch compilation;MaJIC provides an interactive frontend that looks like MATLAB and compiles/optimizes code behind the scenes in real time, employing a combination of just-in-time and speculative ahead-of-time compilation. Performance results show that the proper mixture of these two techniques can yield near-zero response time as well as performance gains previously achieved only by batch compilers.

关键词： design languages algorithms performance

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Proceedings of the acm sigplan conference on programming language design and implementation (pldi)

Proceedings of the ACM SIGPLAN conference on programming lan...

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acm sigplan'01 conference on programming language design and implementation (pldi)

The proceedings contains 30 papers from the Proceedings of the acm sigplan conference on programming language and implementation (pldi). Topics discussed include: design and implementation of generics for the .NET common language runtime;dynamic software updating;demand-driven pointer analysis;incrementalized pointer and escape analysis;enforcing high-level protocols in low-level software;language support for regions;principled scavenging;heap profiling for space-efficient Java;composing high-performance memory allocators;and the pointer assertion logic engine.

关键词： Computer programming languages

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Efficient and precise datarace detection for multithreaded object-oriented programs

Efficient and precise datarace detection for multithreaded o...

引用

conference on programming language design and implementation (pldi 02)

作者： Choi, JD Lee, KW Loginov, A O'Callahan, R Sarkar, V Sridharan, M IBM Corp Thomas J Watson Res Ctr Yorktown Hts NY 10598 USA Univ Washington Seattle WA 98195 USA Univ Wisconsin Madison WI 53706 USA MIT Cambridge MA 02139 USA

We present a novel approach to dynamic datarace detection for multithreaded object-oriented programs. Past techniques for on-the-fly datarace detection either sacrificed precision for performance, leading to many false positive datarace reports, or maintained precision but incurred significant overheads in the range of 3x to 30x. In contrast, our approach results in very few false positives and runtime overhead in the 13% to 42% range, making it both efficient and precise. This performance improvement is the result of a unique combination of complementary static and dynamic optimization techniques.

关键词： experimentation languages measurement performance dataraces race conditions debugging parallel programs synchronization multithreaded programming object-oriented programming static-dynamic co-analysis

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Adoption and focus:: Practical linear types for imperative programming 02

Adoption and focus:: Practical linear types for imperative p...

引用

conference on programming language design and implementation (pldi 02)

作者： Fähndrich, M DeLine, R Microsoft Res Redmond WA 98052 USA

ISBN: (纸本)9781581134636

A type system with linearity is useful for checking software protocols and resource management at compile time. Linearity provides powerful reasoning about state changes, but at the price of restrictions on aliasing. The hard division between linear and nonlinear types forces the programmer to make a trade-off between checking a protocol on an object and aliasing the object. Most onerous is the restriction that any type with a linear component must itself be linear. Because of this, checking a protocol on an object imposes aliasing restrictions on any data structure that directly or indirectly points to the object. We propose a new type system that reduces these restrictions with the adoption and focus constructs. Adoption safely allows a programmer to alias objects on which she is checking protocols, and focus allows the reverse. A programmer can alias data structures that point to linear objects and use focus for safe access to those objects. We discuss how we implemented these ideas in the Vault programming language.

关键词： design languages reliability verification linear types heap aliasing region-based memory management

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A compiler approach to fast hardware design space exploration in FPGA-based systems

A compiler approach to fast hardware design space exploratio...

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conference on programming language design and implementation (pldi 02)

作者： So, B Hall, MW Diniz, PC Univ So Calif Inst Informat Sci Marina Del Rey CA 90292 USA

This paper describes an automated approach to hardware design space exploration, through a collaboration between parallelizing compiler technology and high-level synthesis tools. We present a compiler algorithm that automatically explores the large design spaces resulting from the application of several program transformations commonly used in application-specific hardware designs. Our approach uses synthesis estimation techniques to quantitatively evaluate alternate designs for a loop nest computation. We have implemented this design space exploration algorithm in the context of a compilation and synthesis system called DE-FACTO, and present results of this implementation on five multimedia kernels. Our algorithm derives an implementation that closely matches the performance of the fastest design in the design space, and among implementations with comparable performance, selects the smallest design. We search on average only 0.3% of the design space. This technology thus significantly raises the level of abstraction for hardware design and explores a design space much larger than is feasible for a human designer.

关键词： algorithms performance design experimentationdesign space exploration data dependence analysis reuse analysis loop transformations

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Effective sign extension elimination 02

Effective sign extension elimination

引用

conference on programming language design and implementation (pldi 02)

作者： Kawahito, M Komatsu, H Nakatani, T IBM Tokyo Res Lab Kanagawa 2428502 Japan

ISBN: (纸本)9781581134636

Computer designs are shifting from 32-bit architectures to 64-bit architectures, while most of the programs available today are still designed for 32-bit architectures, Java(TM), for example, specifies the frequently used "int" as a 32-bit data type. If such Java programs are executed on a 64-bit architecture, many 32-bit values must be sign-extended to 64-bit values for integer operations. This causes serious performance overhead. In this paper, we present a fast and effective algorithm for eliminating sign extensions. We implemented this algorithm in the IBM Java Just-in-Time (JIT) compiler for IA-64(TM). Our experimental results show that our algorithm effectively eliminates the majority of sign extensions, They also show that it significantly improves performance, while it increases JIT compilation time by only 0.11%. We implemented our algorithm for programs in Java, but it can be applied to any language requiring sign extensions.

关键词： algorithms performance design experimentation sign extension 64-bit architectures Java JIT compilers IA-64

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Extended static checking for Java 02

Extended static checking for Java

引用

Proceedings of the acm sigplan 2002 conference on programming language design and implementation (pldi'02)

作者： Flanagan, Cormac Leino, K. Rustan M. Lillibridge, Mark Nelson, Greg Saxe, James B. Stata, Raymie Compaq Systems Research Center 130 Lytton Ave. Palo Alto CA 94301 United States

ISBN: (纸本)9781581134636

Software development and maintenance are costly endeavors. The cost can be reduced if more software defects are detected earlier in the development cycle. This paper introduces the Extended Static Checker for Java (ESC/Java), an experimental compile-time program checker that finds common programming errors. The checker is powered by verification-condition generation and automatic theoremproving techniques. It provides programmers with a simple annotation language with which programmer design decisions can be expressed formally. ESC/Java examines the annotated software and warns of inconsistencies between the design decisions recorded in the annotations and the actual code, and also warns of potential runtime errors in the code. This paper gives an overview of the checker architecture and annotation language and describes our experience applying the checker to tens of thousands of lines of Java programs.

关键词： Java programming language

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A system and language for building system-specific, static analyses 02

A system and language for building system-specific, static a...

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conference on programming language design and implementation (pldi 02)

作者： Hallem, S Chelf, B Xie, YC Engler, D Stanford Univ Stanford CA 94305 USA

ISBN: (纸本)9781581134636

This paper presents a novel approach to bug-finding analysis and an implementation of that approach. Our goal is to find as many serious bugs as possible. To do so, we designed a flexible, easy-to-use extension language for specifying analyses and an efficient algorithm for executing these extensions. The language, metal, allows the users of our system to specify a broad class of analyses in terms that resemble the intuitive description of the rules that they check. The system, xgcc, executes these analyses efficiently using a context-sensitive, interprocedural analysis. Our prior work has shown that the approach described in this paper is effective: it has successfully found thousands of bugs in real systems code. This paper describes the underlying system used to achieve these results. We believe that our system is an effective framework for deploying new bug-finding analyses quickly and easily.

关键词： extensible compilation error detection reliability security verification

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Efficient discovery of regular stride patterns in irregular programs and its use in compiler prefetching

Efficient discovery of regular stride patterns in irregular ...

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conference on programming language design and implementation (pldi 02)

作者： Wu, YF Intel Labs Programming Syst Res Santa Clara CA 95052 USA

Irregular data references are difficult to prefetch, as the future memory address of a load instruction is hard to anticipate by a compiler. However, recent studies as well as our experience indicate that some important load instructions in irregular programs contain stride access patterns. Although the load instructions with stride patterns are difficult to identify with static compiler techniques, we developed an efficient profiling method to discover these load instructions. The new profiling method integrates the profiling for stride information and the traditional profiling for edge frequency into a single profiling pass. The integrated profiling pass runs only 17% slower than the frequency profiling alone. The collected stride information helps the compiler to identify load instructions with stride patterns that can be prefetched efficiently and beneficially. We implemented the new profiling and prefetching techniques in a research compiler for Itanium(TM) Processor Family (IPF), and obtained significant performance improvement for the SPECINT2000 programs running on Itanium machines. For example, we achieved a 1.59x speedup for *** 1.14x for ***, and 1.08x for ***. We also showed that the performance gain is stable across input data sets. These benefits make the new profiling and prefetching techniques suitable for production compilers.

关键词： languages performance design experimentation algorithms integrated stride and frequency profiling data prefetching strongly single-strided loads phased multi-strided loads performance evaluation

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Post-pass binary adaptation for software-based speculative precomputation

Post-pass binary adaptation for software-based speculative p...

引用

conference on programming language design and implementation (pldi 02)

作者： Liao, SSW Wang, PH Wang, H Hoflehner, G Lavery, D Shen, JP

Recently, a number of thread-based prefetching techniques have been proposed. These techniques aim at improving the latency of single-threaded applications by leveraging multithreading resources to perform memory prefetching via speculative prefetch threads. Software-based speculative precomputation (SSP) is one such technique, proposed for multithreaded Itanium models. SSP does not require expensive hardware support-instead it relies on the compiler to adapt binaries to perform prefetching on otherwise idle hardware thread contexts at run time. This paper presents a post-pass compilation tool for generating SSP-enhanced binaries. The tool is able to: (1) analyze a single-threaded application to generate prefetch threads;(2) identify and embed trigger points in the original binary;and (3) produce a new binary that has the prefetch threads attached. The execution of the new binary spawns the speculative prefetch threads, which are executed concurrently with the main thread. Our results indicate that for a set of pointer-intensive benchmarks, the prefetching performed by the speculative threads achieves an average of 87% speedup on an in-order processor and 5% speedup on an out-of-order processor.

关键词： measurement performance design experimentation algorithms long-range thread-based prefetching pointer slicing slack chaining speculative precomputation speculation prediction scheduling postpass dependence reduction loop rotation delay minimization triggering

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