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acm sigplan conference on programming language design and implementation

作者： Jeff Huang Charles Zhang Julian Dolby Hong Kong University of Science and Technology IBM Thomas J. Watson Research Center

ISBN: (纸本)9781450320146

We present CLAP, a new technique to reproduce concurrency bugs. CLAP has two key steps. First, it logs thread local execution paths at runtime. Second, offline, it computes memory dependencies that accord with the logged execution and are able to reproduce the observed bug. The second step works by combining constraints from the thread paths and constraints based on a memory model, and computing an execution with a constraint solver. CLAP has four major advantages. First, logging purely local execution of each thread is substantially cheaper than logging memory interactions, which enables CLAP to be efficient compared to previous approaches. Second, our logging does not require any synchronization and hence with no added memory barriers or fences; this minimizes perturbation and missed bugs due to extra synchronizations foreclosing certain racy behaviors. Third, since it uses no synchronization, we extend CLAP to work on a range of relaxed memory models, such as TSO and PSO, in addition to sequential consistency. Fourth, CLAP can compute a much simpler execution than the original one, that reveals the bug with minimal thread context switches. To mitigate the scalability issues, we also present an approach to parallelize constraint solving, which theoretically scales our technique to programs with arbitrary execution length. Experimental results on a variety of multithreaded benchmarks and real world concurrent applications validate these advantages by showing that our technique is effective in reproducing concurrency bugs even under relaxed memory models; furthermore, it is significantly more efficient than a state-of-the-art technique that records shared memory dependencies, reducing execution time overhead by 45% and log size by 88% on average.

关键词： Concurrency Bug Reproduction Local Execution Constraint Solving Algorithms design Performance Theory

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design a game of charged particles moving in a uniform magnetic field based on unity 3D-Take "the wise snake through the pass" as an example 2021

Design a game of charged particles moving in a uniform magne...

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6th International conference on Distance Education and Learning, ICDEL 2021

作者： Qiu, Shuang Zhang, Feng Peng, Zhao-Yang College of Physics and Electronic Information Yunnan Normal University Kunmming650500 China

ISBN: (纸本)9781450390033

Educational games are hot spots in the field of education, and they are widely concerned by scholars. Educational games can prompt students to understand and grasp knowledge in the process of participating in the game. Since Unity3d is the mainstream game development software, educators should think about how to use it to design a game that aims at the current teaching difficulties to supplement daily teaching. The motion of charged particles in uniform magnetic field is the focus of physics course in senior high school. Most of the students said that they felt inadequate when solving problems that required them to depict the topic of the electric particle movement trajectory. In view of the actual situation of the above students, this paper uses the Unity engine, C # programming language and the relevant education theory related to education game designing to design a 2D game. The purpose is to make students understand the trajectory of charged particles in the uniform magnetic field in the process of participating in the game, and then learn the relevant knowledge of electromagnetic part better. © 2021 acm.

关键词： Charged particles

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Tradeoffs in transactional memory virtualization

Tradeoffs in transactional memory virtualization

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12th International conference on Architectural Support for programming languages and Operating Systems

作者： Chung, JaeWoong Minh, Chi Cao McDonald, Austen Skare, Travis Chafi, Hassan Carlstrom, Brian D. Kozyrakis, Christos Olukotun, Kunle Stanford Univ Comp Syst Lab Stanford CA 94305 USA

For transactional memory (TM) to achieve widespread acceptance, transactions should not be limited to the physical resources of any specific hardware implementation. TM systems should guarantee correct execution even when transactions exceed scheduling quanta, overflow the capacity of hardware caches and physical memory, or include more independent nesting levels than what is supported in hardware. Existing proposals for TM virtualization are either incomplete or rely on complex hardware implementations, which are an overkill if virtualization is invoked infrequently in the common case. We present eXtended Transactional Memory (XTM), the first TM virtualization system that virtualizes all aspects of transactional execution (time, space, and nesting depth). XTM is implemented in software using virtual memory support. It operates at page granularity, using private copies of overflowed pages to buffer memory updates until the transaction commits and snapshots of pages to detect interference between transactions. We also describe two enhancements to XTM that use limited hardware support to address key performance bottlenecks. We compare XTM to hardware-based virtualization using both real applications and synthetic microbenchmarks. We show that despite being software-based, XTM and its enhancements are competitive with hardware-based alternatives. Overall, we demonstrate that XTM provides a complete, flexible, and low-cost mechanism for practical TM virtualization.

关键词： design performance chip multi-processor OS support transactional memory virtualization

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Mdspan in C++: A Case Study in the Integration of Performance Portable Features into International language Standards

Mdspan in C++: A Case Study in the Integration of Performanc...

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2019 IEEE/acm International Workshop on Performance, Portability and Productivity in HPC, P3HPC 2019

作者： Hollman, David Lelbach, Bryce Edwards, H. Carter Hoemmen, Mark Sunderland, Daniel Trott, Christian R. Scalable Modeling and Analysis Sandia National Laboratories LivermoreCA United States NVIDIA Corp. Santa ClaraCA United States Engineering Sciences Sandia National Laboratories AlbuquerqueNM United States Center for Computing Research Sandia National Laboratories AlbuquerqueNM United States

ISBN: (纸本)9781728160030

Multi-dimensional arrays are ubiquitous in high-performance computing (HPC), but their absence from the C++ language standard is a long-standing and well-known limitation of their use for HPC. This paper describes the design and implementation of mdspan, a proposed C++ standard multidimensional array view (planned for inclusion in C++23). The proposal is largely inspired by work done in the Kokkos project - a C++ performance-portable programming model de- ployed by numerous HPC institutions to prepare their code base for exascale-class supercomputing systems. This paper describes the final design of mdspan af- ter a five-year process to achieve consensus in the C++ community. In particular, we will lay out how the design addresses some of the core challenges of performance-portable programming, and how its cus- tomization points allow a seamless extension into areas not currently addressed by the C++ Standard but which are of critical importance in the heterogeneous computing world of today's systems. Finally, we have provided a production-quality implementation of the proposal in its current form. This work includes several benchmarks of this implementation aimed at demon- strating the zero-overhead nature of the modern design. © 2019 IEEE.

关键词： C++ (programming language)

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Parametric polymorphism for Java: a reflective solution 98

Parametric polymorphism for Java: a reflective solution

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Proceedings of the 13th acm sigplan conference on Object-oriented programming, systems, languages, and applications

作者： Jose H. Solorzano Suad Alagić Computer Science Department Wichita State University Wichita KS

ISBN: (纸本)9781581130058

A number of inadequacies of existing implementation techniques for extending Java™ with parametric polymorphism are revealed. Homogeneous translations are the most space-efficient but they are not compatible with reflection, some models of persistence, and multiple dispatch. Heterogeneous translations, on the other hand, can potentially produce large amounts of redundant information. implementation techniques that address these concerns are developed. In languages that support run-time reflection, an adequate implementation of parametric, bounded and F-bounded polymorphism is shown to require (reflective) run-time support. In Java, extensions to the core classes are needed. This is in spite of the fact that parametric polymorphism is intended to be managed statically.

关键词： language design and implementation reflection persistence

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Tales from the Jungle 12

Tales from the Jungle

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acm Special Interest Group on programming languages International conference on Functional programming

作者： Peter Sewell University of Cambridge

ISBN: (纸本)9781450310543

We rely on a computational infrastructure that is a densely inter-wined mass of software and hardware: programming languages, network protocols, operating systems, and processors. It has accumulated great complexity, from a combination of engineering design decisions, contingent historical choices, and sheer scale, yet it is defined at best by prose specifications, or, all too often, just by the common implementations. Can we do better? More specifically, can we apply rigorous methods to this mainstream infrastructure, taking the accumulated complexity seriously, and if we do, does it help? My colleagues and I have looked at these questions in several contexts: the TCP/IP network protocols with their Sockets API; programming language design, including the Java module system and the C11/C++11 concurrency model; the hardware concurrency behaviour of x86, IBM POWER, and ARM multiprocessors: and compilation of concurrent code. In this talk I will draw some lessons from what did and did not succeed, looking especially at the empirical nature of some of the work, at the social process of engagement with the various different communities, and at the mathematical and software tools we used. Domain-specific modelling languages (based on functional programming ideas) and proof assistants were invaluable for work- ing with the large and loose specifications involved: idioms within HOL4 for TCP, our Ott tool for programming language specification, and Owens's Lem tool for portable semantic definitions, with HOL4, Isabelle, and Coq, for the relaxed-memory concurrency semantics work. Our experience with these suggests something of what is needed to make full-scale rigorous semantics a commonplace reality.

关键词： Mainstream systems Jungles Network protocols Tales Narration Semantics Computer programming languages Software Tools Specifications design engineering Concurrency Collected papers PROCESSOR

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Scalable Address Spaces Using RCU Balanced Trees

Scalable Address Spaces Using RCU Balanced Trees

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17th International conference on Architectural Support for programming languages and Operating Systems

作者： Clements, Austin T. Kaashoek, M. Frans Zeldovich, Nickolai MIT CSAIL Cambridge MA USA

ISBN: (纸本)9781450307598

Software developers commonly exploit multicore processors by building multithreaded software in which all threads of an application share a single address space. This shared address space has a cost: kernel virtual memory operations such as handling soft page faults, growing the address space, mapping files, etc. can limit the scalability of these applications. In widely-used operating systems, all of these operations are synchronized by a single per-process lock. This paper contributes a new design for increasing the concurrency of kernel operations on a shared address space by exploiting read-copy-update (RCU) so that soft page faults can both run in parallel with operations that mutate the same address space and avoid contending with other page faults on shared cache lines. To enable such parallelism, this paper also introduces an RCU-based binary balanced tree for storing memory mappings. An experimental evaluation using three multithreaded applications shows performance improvements on 80 cores ranging from 1.7 x to 3.4 x for an implementation of this design in the Linux 2.6.37 kernel. The RCU-based binary tree enables soft page faults to run at a constant cost with an increasing number of cores, suggesting that the design will scale well beyond 80 cores.

关键词： Algorithms design Performance RCU Virtual memory Multicore Lock-free algorithms Concurrent balanced trees Scalability

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Inter-Core Cooperative TLB Prefetchers for Chip Multiprocessors

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acm sigplan NOTICES 2010年第3期45卷 359-370页

作者： Bhattacharjee, Abhishek Martonosi, Margaret Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

Translation Lookaside Buffers (TLBs) are commonly employed in modern processor designs and have considerable impact on overall system performance. A number of past works have studied TLB designs to lower access times and miss rates, specifically for uniprocessors. With the growing dominance of chip multiprocessors (CMPs), it is necessary to examine TLB performance in the context of parallel workloads. This work is the first to present TLB prefetchers that exploit commonality in TLB miss patterns across cores in CMPs. We propose and evaluate two Inter-Core Cooperative (ICC) TLB prefetching mechanisms, assessing their effectiveness at eliminating TLB misses both individually and together. Our results show these approaches require at most modest hardware and can collectively eliminate 19% to 90% of data TLB (D-TLB) misses across the surveyed parallel workloads. We also compare performance improvements across a range of hardware and software implementation possibilities. We find that while a fully-hardware implementation results in average performance improvements of 8-46% for a range of TLB sizes, a hardware/software approach yields improvements of 4-32%. Overall, our work shows that TLB prefetchers exploiting inter-core correlations can effectively eliminate TLB misses.

关键词： design Experimentation Performance Translation Lookaside Buffer Parallelism Prefetching

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The design and implementation of a certifying compiler 98

The design and implementation of a certifying compiler

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Proceedings of the acm sigplan 1998 conference on programming language design and implementation

作者： George C. Necula Peter Lee School of Computer Science Carnegie Mellon University Pittsburgh Pennsylvania

ISBN: (纸本)9780897919876

This paper presents the design and implementation of a compiler that translates programs written in a type-safe subset of the C programming language into highly optimized DEC Alpha assembly language programs, and a certifier that automatically checks the type safety and memory safety of any assembly language program produced by the compiler. The result of the certifier is either a formal proof of type safety or a counterexample pointing to a potential violation of the type system by the target program. The ensemble of the compiler and the certifier is called a certifying *** advantages of certifying compilation over previous approaches can be claimed. The notion of a certifying compiler is significantly easier to employ than a formal compiler verification, in part because it is generally easier to verify the correctness of the result of a computation than to prove the correctness of the computation itself. Also, the approach can be applied even to highly optimizing compilers, as demonstrated by the fact that our compiler generates target code, for a range of realistic C programs, which is competitive with both the cc and gcc compilers with all optimizations enabled. The certifier also drastically improves the effectiveness of compiler testing because, for each test case, it statically signals compilation errors that might otherwise require many executions to detect. Finally, this approach is a practical way to produce the safety proofs for a Proof-Carrying Code system, and thus may be useful in a system for safe mobile code.

关键词：

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The transformational government framework 11

The transformational government framework

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5th International conference on Theory and Practice of Electronic Governance, ICEGOV 2011

作者： Borras, John A. OASIS TGF Technical Committee Wendron Close Woking Surrey United Kingdom

ISBN: (纸本)9781450307468

The Transformational Government Framework (TGF) is the first practical "how to" standard for the design and implementation of an effective program of technology-enabled change at national, state or local government level. It describes a managed process of ICT-enabled change in the public sector, which puts the needs of citizens and businesses at the heart of that process and which achieves significant and transformational impacts on the efficiency and effectiveness of government. During much of the last two decades, many Governments thought that new technology would provide the key to deliver the necessary transformations to enable them to deliver more with less. But at a time when virtually every government is now an "egovernment", it is now clear that ICT is no magic bullet. Duplicated expenditure, wasted resources, no critical mass of users for online services, and limited impact on core public policy objectives - this has been the reality of many countries' experience of e-Government. This paper outlines the work of the OASIS Technical Committee established to address this new approach by developing a new framework and set of enabling standards that can jump-start this transformation and optimize the benefits of technology-enabled change at all levels of government. The various components of the Transformational Government Framework described in this paper represent the first outputs of the committee - the TGF Primer [1] and the TGF Pattern language [2]. Copyright 2011 acm.

关键词： Computer programming

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