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Proceedings of the acm-sigplan symposium on The ADA programming language

作者： L. J. Groves W. J. Rogers

ISBN: (纸本)9780897910309

An implementation of Ada should be based on a machine-independent translator generating code for a Virtual Machine, which can be realised on a variety of machines. This approach, which leads to a high degree of compiler portability, has been very successful in a number of recent language implementation projects and is the approach which has been specified by the U.S. Army and Air Force in their requirements for Ada *** paper discusses the rationale, requirements and design of such a Virtual Machine for Ada. The discussion concentrates on a number of fundamental areas in which problems arise: basic Virtual Machine structure, including storage structure and addressing; data storage and manipulation; flow of control; subprograms, blocks and exceptions; and task handling.

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A design and implementation of chinese university virtual entrepreneurship education platform system based on B/S structure 2

A design and implementation of chinese university virtual en...

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2nd International conference on Algorithms, Computing and Artificial Intelligence, ACAI 2019

作者： Xia, Yuan Yao, Yi Institute of Educational Economy and Management University of Science and Technology Beijing China Department of Business Administration Yangtze University College of Arts and Science Hubei China

ISBN: (纸本)9781450372619

With the rapid development of network information technology and its wide application in various fields, the practical teaching link of college entrepreneurship education must be closely integrated with modern information technology, from content and form to better adapt to the information age. Development needs. Entrepreneurship education in colleges and universities can not only deepen the reform of higher education, but also provide an important platform for cultivating compound talents with innovative entrepreneurship. The construction of virtual network platform system for entrepreneurship education in colleges has the advantages of openness, unity and sharing. It integrates various business resources to provide students with better and convenient personalized services and the other entrepreneurship. The limitations of the educational network platform. This platform uses the popular B/S structure model, three-layer model design, and applies Microsoft's *** technology platform and joint programming language to focus on the analysis, design, development and implementation process of college entrepreneurship education system. Online teaching platforms in Europe and the United States have already formed scale and achieved great success, such as WEBCT, Blackboard, Virtual-U and other well-known online teaching platforms. Online teaching platforms started late in China, such as Aopeng Education Platform, 4A Online Teaching Platform, and Universal Online Education Platform, etc., but the overall status quo is still in the primary stage of tracking foreign models and development, sharing, network operation efficiency, interaction, Source code, details, and other related factors, as well as the high costs and irreversible factors involved in entrepreneurship education and practical training, these have seriously affected the cultivation of practical teaching and practical ability in innovative entrepreneurship education in universities, which is difficult to meet

关键词： Software design

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A new idiom recognition framework for exploiting hardware-assist instructions

A new idiom recognition framework for exploiting hardware-as...

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12th International conference on Architectural Support for programming languages and Operating Systems

作者： Kawahito, Motohiro Komatsu, Hideaki Moriyama, Takao Inoue, Hiroshi Nakatani, Toshio IBM Tokyo Res Lab Kanagawa 2428502 Japan

Modern processors support hardware-assist instructions (such as TRT and TROT instructions on IBM zSeries) to accelerate certain functions such as delimiter search and character conversion. Such special instructions have often been used in high performance libraries, but they have not been exploited well in optimizing compilers except for some limited cases. We propose a new idiom recognition technique derived from a topological embedding algorithm [4] to detect idiom patterns in the input program more aggressively than in previous approaches. Our approach can detect a pattern even if the code segment does not exactly match the idiom. For example, we can detect a code segment that includes additional code within the idiom pattern. We implemented our new idiom recognition approach based on the Java Just-In-Time (JIT) compiler that is part of the J9 Java Virtual Machine, and we supported several important idioms for special hardware-assist instructions on the IBM zSeries and on some models of the IBM pSeries. To demonstrate the effectiveness of our technique, we performed two experiments. The first one is to see how many more patterns we can detect compared to the previous approach. The second one is to see how much performance improvement we can achieve over the previous approach. For the first experiment, we used the Java Compatibility Kit (JCK) API tests. For the second one we used IBM XML parser, SPECjvm98, and SPCjbb2000. In summary, relative to a baseline implementation using exact pattern matching, our algorithm converted 75% more loops in JCK tests. We also observed significant performance improvement of the XML parser by 64%, of SPECjvm98 by 1%, and of SPECjbb2000 by 2% on average on a z990. Finally, we observed the JIT compilation time increases by only 0.32% to 0.44%.

关键词： algorithms performance design experimentation idiom recognition hardware-assist instructions VMX topological embedding Java JIT

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Engineering with logic: HOL specification and symbolic-evaluation testing for TCP implementations

Engineering with logic: HOL specification and symbolic-evalu...

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作者： Bishop, Steve Fairbairn, Matthew Norrish, Michael Sewell, Peter Smith, Michael Wansbrough, Keith University of Cambridge Computer Laboratory NICTA Canberra

ISBN: (纸本)1595930272

The TCP/IP protocols and Sockets API underlie much of modern computation, but their semantics have historically been very complex and ill-defined. The real standard is the de facto one of the common implementations, including, for example, the 15 000-20 000 lines of C in the BSD implementation. Dealing rigorously with the behaviour of such bodies of code is challenging. We have recently developed a post-hoc specification of TCP, UDP, and Sockets that is rigorous, detailed, readable, has broad coverage, and is remarkably accurate. In this paper we describe the novel techniques that were required. Working within a general-purpose proof assistant (HOL), we developed language idioms (within higher-order logic) in which to write the specification: operational semantics with nondeterminism, time, system calls, monadic relational programming, etc. We followed an experimental semantics approach, validating the specification against several thousand traces captured from three implementations (FreeBSD, Linux, and WinXP). Many differences between these were identified, and a number of bugs. Validation was done using a special-purpose symbolic model checker programmed above HOL. We suggest that similar logic engineering techniques could be applied to future critical software infrastructure at design time, leading to cleaner designs and (via specification-based testing using a similar checker) more predictable implementations. Copyright © 2006 acm.

关键词： Logic programming

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Devil: An IDL for hardware programming 4

Devil: An IDL for hardware programming

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4th conference on Symposium on Operating System design and implementation, OSDI 2000

作者： Mérillon, Fabrice Réveillére, Laurent Consel, Charles Marlet, Renaud Muller, Gilles Compose Group IRISA INRIA University of Rennes I Campus Universitaire de Beaulieu Rennes CedexF-35042 France LaBRI ENSERB 351 cours de la Libération Talence CedexF-33405 France Trusted Logic 5 rue du Bailliage VersaillesF-78000 France

To keep up with the frantic pace at which devices come out, drivers need to be quickly developed, debugged and tested. Although a driver is a critical system component, the driver development process has made little (if any) progress. The situation is particularly disastrous when considering the hardware operating code (i.e., the layer interacting with the device). Writing this code often relies on inaccurate or incomplete device documentation and involves assembly-level operations. As a result, hardware operating code is tedious to write, prone to errors, and hard to debug and maintain. This paper presents a new approach to developing hardware operating code based on an Interface Definition language (IDL) for hardware functionalities, named Devil. This IDL allows a high-level definition of the communication with a device. A compiler automatically checks the consistency of a Devil definition and generates efficient low-level code. Because the Devil compiler checks safety critical properties, the long-awaited notion of robustness for hardware operating code is made possible. Finally, the wide variety of devices that we have already specified (mouse, sound, DMA, interrupt, Ethernet, video, and IDE disk controllers) demonstrates the expressiveness of the Devil language.

关键词： Program compilers

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LLVM Compiler implementation for explicit parallelization and SIMD vectorization 4

LLVM Compiler implementation for explicit parallelization an...

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4th Workshop on the LLVM Compiler Infrastructure in HPC, LLVM-HPC 2017 - Held in conjunction with the International conference for High Performance Computing, Networking, Storage and Analysis, SC 2017

作者： Tian, Xinmin Saito, Hideki Su, Ernesto Lin, Jin Guggilla, Satish Caballero, Diego Masten, Matt Savonichev, Andrew Rice, Michael Demikhovsky, Elena Zaks, Ayal Rapaport, Gil Gaba, Abhinav Porpodas, Vasileios Garcia, Eric Intel Corporation 3600 Juliette Lane Santa ClaraCA95054 United States

ISBN: (纸本)9781450355650

With advances of modern multi-core processors and accelerators, many modern applications are increasingly turning to compilerassisted parallel and vector programming models such as OpenMP, OpenCL, Halide, Python and TensorFlow. It is crucial to ensure that LLVM-based compilers can optimize parallel and vector code as effectively as possible. In this paper, we first present a set of updated LLVM IR extensions for explicitly parallel, vector, and offloading program constructs in the context of C/C++/OpenCL. Secondly, we describe our LLVM design and implementation for advanced features in OpenMP such as parallel loop reduction, task and taskloop, SIMD loop and functions, and we discuss the impact of our updated implementation on existing LLVM optimization passes. Finally, we present a re-use case of our infrastructure to enable explicit parallelization and vectorization extensions in our OpenCL compiler to achieve ~35x performance speedup for a wellknown autonomous driving workload on a multi-core platform configured with Intel(r) Xeon(r) Scalable Processors. © 2017 Association for Computing Machinery.

关键词： C++ (programming language)

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Automatic abstraction of real-time software and re-implementation in Ada

Automatic abstraction of real-time software and re-implement...

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1991 conference on TRI-Ada: Today's Accomplishments;Tomorrow's Expectations, TRI-Ada 1991

作者： Prywes, Noah Lock, Evan Ge, Xiang Computer Command and Control Company 2300 Chestnut Street Ste. 230 PhiladelphiaPA19103 United States

ISBN: (纸本)0897914457

The paper reports on the underlying concepts of a system for software reverse engineering. Although, the immediate goal is translation from CMS-2 to Ada, the system is envisaged more broadly as a comprehensive environment for the software lifecycle: for initial development, maintenance, re-engineering and re-documentation. This environment must assure consistency at all times of design, programs and documentation. The paper describes the three phases of the system: Extracting design and documentation from existing software. User visualization and design/redesign of the software. Ada program generation from design/redesign. The first phase translates source programs into an object-oriented Entity-Relation-Attribute (ERA) diagram, which is the main vehicle for the graphic visualization. The translation uses a concise set of objects and relations. The second phase consists of user query and retrieval of subdiagrams that provide views of the software, needed to visualize or redesign specific aspects of the software. This phase is divided into in-the-large and in-the-small parts. The in-the-large part involves high level objects such as: systems, packages, tasks, procedures (or functions), external variables, input/output and comments that specify requirements or provide explanations. The user may need to use design tools that optimize the design. The in-the-small part consists of execution statements within an individual program unit. These are translated into the MODEL equational language and visualized through a petri-net like graph. The equational representation is considerably easier to comprehend, test and verify. Finally, the code generation phase uses the graphics and text from the previous phase to generate respective parts of Ada programs. There are three code generators, as follows: Packages are generated from object usage views. Tasks are generated from dataflow views. Individual procedures are generated from equations and petri-net like diagrams. The approac

关键词： Codes (symbols)

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RaTrace: Simple and efficient abstractions for BVH ray traversal algorithms

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acm sigplan Notices 2017年第12期52卷 157-168页

作者： Pérard-Gayot, Arsène Weier, Martin Membarth, Richard Slusallek, Philipp Leißa, Roland Hack, Sebastian Computer Graphics Lab Saarland University Saarbrücken Germany Institute of Visual Computing Bonn-Rhein-Sieg University Sankt Augustin Germany Agents and Simulated Reality DFKI Saarbrücken Germany Compiler Design Lab Saarland University Saarbrücken Germany

In order to achieve the highest possible performance, the ray traversal and intersection routines at the core of every high-performance ray tracer are usually hand-coded, heavily optimized, and implemented separately for each hardware platform - even though they share most of their algorithmic core. The results are implementations that heavily mix algorithmic aspects with hardware and implementation details, making the code non-portable and difficult to change and maintain. In this paper, we present a new approach that offers the ability to define in a functional language a set of conceptual, high-level language abstractions that are optimized away by a special compiler in order to maximize performance. Using this abstraction mechanism we separate a generic ray traversal and intersection algorithm from its low-level aspects that are specific to the target hardware. We demonstrate that our code is not only significantly more flexible, simpler to write, and more concise but also that the compiled results perform as well as state-of-the-art implementations on any of the tested CPU and GPU platforms. © 2017 acm.

关键词： Functional programming

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Geiger: Monitoring the buffer cache in a virtual machine environment

Geiger: Monitoring the buffer cache in a virtual machine env...

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12th International conference on Architectural Support for programming languages and Operating Systems

作者： Jones, Stephen T. Arpaci-Dusseau, Andrea C. Arpaci-Dusseau, Remzi H. Univ Wisconsin Dept Comp Sci Madison WI 53706 USA

Virtualization is increasingly being used to address server management and administration issues like flexible resource allocation, service isolation and workload migration. In a virtualized environment, the virtual machine monitor (VMM) is the primary resource manager and is an attractive target for implementing system features like scheduling, caching, and monitoring. However, the lack of runtime information within the VMM about guest operating systems, sometimes called the semantic gap, is a significant obstacle to efficiently implementing some kinds of services. In this paper we explore techniques that can be used by a VMM to passively infer useful information about a guest operating system's unified buffer cache and virtual memory system. We have created a prototype implementation of these techniques inside the Xen VMM called Geiger and show that it can accurately infer when pages are inserted into and evicted from a system's buffer cache. We explore several nuances involved in passively implementing eviction detection that have not previously been addressed, such as the importance of tracking disk block liveness, the effect of file system journaling, and the importance of accounting for the unified caches found in modern operating systems. Using case studies we show that the information provided by Geiger enables a VMM to implement useful VMM-level services. We implement a novel working set size estimator which allows the VMM to make more informed memory allocation decisions. We also show that a VMM can be used to drastically improve the hit rate in remote storage caches by using eviction-based cache placement without modifying the application or operating system storage interface. Both case studies hint at a future where inference techniques enable a broad new class of VMM-level functionality.

关键词： design measurement performance virtual machine inference

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Aggressive inlining 97

Aggressive inlining

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Proceedings of the acm sigplan 1997 conference on programming language design and implementation

作者： Andrew Ayers Richard Schooler Robert Gottlieb Hewlett-Packard Massachusetts Language Laboratory 300 Apollo Drive Chelmsford MA

ISBN: (纸本)9780897919074

Existing research understates the benefits that can be obtained from inlining and cloning, especially when guided by profile information. Our implementation of inlining and cloning yields excellent results on average and very rarely lowers performance. We believe our good results can be explained by a number of factors: inlining at the intermediate-code level removes most technical restrictions on what can be inlined; the ability to inline across files and incorporate profile information enables us to choose better inline candidates; a high-quality back end can exploit the scheduling and register allocation opportunities presented by larger subroutines; an aggressive processor architecture benefits from more predictable branch behavior; and a large instruction cache mitigates the impact of code expansion. We describe the often dramatic impact of our inlining and cloning on performance: for example, the implementations of our inlining and cloning algorithms in the HP-UX 10.20 compilers boost SPECint95 performance on a PA8000-based workstation by a factor of 1.32.

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