There are two trends in the software initiatives of the U. S. Department of Defense which will have direct impact on future software development and which suggest a focus for current basic research in software. These ...
ISBN:
(纸本)9780897912181
There are two trends in the software initiatives of the U. S. Department of Defense which will have direct impact on future software development and which suggest a focus for current basic research in software. These trends are 1) the move toward smart weapons, suggesting the use of Expert Systems to control these weapons, and 2) the directive that all software for embedded computer systems be written in Ada. The research focus suggested by these developments is an analysis of the Ada programminglanguage and its associated programming support environment (APSE) to determine how to design and construct an Expert System for natural implementation in *** is well known that Ada can be used as a language for Expert Systems. There now exist several Expert System Shells written in Ada and more are being developed every day. The issue still open to research is how to do this optimally, making the best use of the expressive power of the language. An absurd example will make this clearer. It is also known that it is possible to write an Expert System in COBOL. Doing such would be a very tedious and error prone task, because the expressive power of the COBOL language is focused on commercial *** possibility for writing an Expert System in Ada would be to take an existing Expert System in LISP and translate the code, line for line into Ada. Admittedly this is a plausible task; this author has done some preliminary investigation in this area. However, it is arguable that such an approach will not result in efficient Ada code, for constructs which are natural to LISP might not translate into constructs natural to *** it is difficult to give a precise definition of an Expert System, it is easy to list characteristics which are usually associated with such a system. This paper presents the results of some preliminary research on the implementation of these features by means of some of the structures in Ada, such as Generic Program Units, Packages and Data
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most designs are described in a hardware d...
ISBN:
(纸本)9780769514413
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most designs are described in a hardware description language (HDL), like Verilog or VHDL, usually this problem is solved in the Boolean domain, using Boolean solvers. These engines often show a poor performance for data path verification. Instead of solving the problem at the bit-level, a method is proposed to transform conjunctions of bitvector equalities and inequalities into sets of integer linear arithmetic constraints. It is shown that it is possible to correctly model the modulo semantics of HDL operators as linear constraints. Integer linear constraint solvers are used as a decision procedure for bitvector arithmetic. In the implementation we focus on verification of arithmetic properties of Verilog-HDL designs. Experimental results show considerable performance advantages over high-end Boolean SAT solver approaches. The speed-up on the benchmarks studied is several orders of magnitude.
CORAL is a deductive database system that supports a rich declarative language, provides a wide range of evaluation methods, and allows a combination of declarative and imperative programming. The data can be persiste...
ISBN:
(纸本)9780897915922
CORAL is a deductive database system that supports a rich declarative language, provides a wide range of evaluation methods, and allows a combination of declarative and imperative programming. The data can be persistent on disk or can reside in main-memory. We describe the architecture and implementation of *** were two important goals in the design of the CORAL architecture: (1) to integrate the different evaluation strategies in a reasonable fashion, and (2) to allow users to influence the optimization techniques used so as to exploit the full power of the CORAL implementation. A CORAL declarative program can be organized as a collection of interacting modules and this modular structure is the key to satisfying both these goals. The high level module interface allows modules with different evaluation techniques to interact in a transparent fashion. Further, users can optionally tailor the execution of a program by selecting from among a wide range of control choices at the level of each *** also has an interface with C++, and users can program in a combination of declarative CORAL, and C++ extended with CORAL primitives. A high degree of extensibility is provided by allowing C++ programmers to use the class structure of C++ to enhance the CORAL implementation.
We present RustSim, a library for discrete-event process-oriented simulations designed and implemented in the Rust programminglanguage. It includes a broad set of classes to allow the user to implement simulation pro...
ISBN:
(纸本)9798350369663
We present RustSim, a library for discrete-event process-oriented simulations designed and implemented in the Rust programminglanguage. It includes a broad set of classes to allow the user to implement simulation processes and process-oriented primitives. The flexible modular design of RustSim allows users to extend its functionality. In addition, RustSim includes mechanisms to avoid inconsistencies when applying state-changing primitives that other libraries in the language's ecosystem do not provide. We take advantage of Rust generators (coroutine equivalents) to implement process-oriented simulation primitives. Finally, the library's internal process handling structure is discussed in detail, including its implementation, how simulations are executed, and a case study with a highly detailed example of its use.
sd&m AG, software design & management, has the development and integration of custom built information systems for business critical processes as its area of business. IT consulting with engineering and implem...
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sd&m AG, software design & management, has the development and integration of custom built information systems for business critical processes as its area of business. IT consulting with engineering and implementation competence makes it complete. Our clients are major companies and organizations. They want to achieve a competitive edge by implementing custom built solutions. The core competence of the 1.600 person company is the design of IT architectures and the realization of complex projects in a cooperative way with clients. The overall key success factor is the qualification of the team. Continuously to manage is the growth including small acquisitions, the dynamic of technology and the increasing expectations of our clients. For our clients we are innovation partner. Our understanding is not to be the earliest possible adapter for the last hype but being able to differentiate between hype and future value. We use two sources for improvement: project experience and innovation management. Project experience: We have implemented continuous cycles of learning and improvement, project experiences and best practices are collected and evaluated by communities and sd&m Research, enriched by scientific methods together with universities. Best practices certified by our best software architects will be finished to excellent solutions and become part of our organized knowledge, can be distributed by our development platform as a solution pattern or component, influence our training schools, flow into publications and community work and sometimes result in a book. Announcement and distribution is one of the key success factors. Innovation management: Results of our innovation management are in a first phase knowledge with small experience about a new programminglanguage or environment, a new integration product suite or a new way to design application systems and their successful integration into complex application landscapes. In the following phase we go to our market
Because of stringent power constraints, aggressive latency-hiding approaches, such as prefetching, are absent in the state-of-the-art embedded processors. There are two main reasons that make prefetching power ineffic...
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Because of stringent power constraints, aggressive latency-hiding approaches, such as prefetching, are absent in the state-of-the-art embedded processors. There are two main reasons that make prefetching power inefficient. First, compiler-inserted prefetch instructions increase code size and, therefore, could increase I-cache power. Second, inaccurate prefetching (especially for hardware prefetching) leads to high D-cache power consumption because of useless accesses. In this work, we show that it is possible to support power-efficient prefetching through bit-differential offset assignment. We target the prefetching of relocatable stack variables with a high degree of precision. By assigning the offsets of stack variables in such a way that most consecutive addresses differ by 1 bit, we can prefetch them with compact prefetch instructions to save I-cache power. The compiler first generates an access graph of consecutive memory references and then attempts a layout of the memory locations in the smallest hypercube. Each dimension of the hypercube represents a 1-bit differential addressing. The embedding is carried out in as compact a hypercube as possible in order to save memory space. Each load/store instruction carries a hint regarding prefetching the next memory reference by encoding its differential address with respect to the current one. To reduce D-cache power cost, we further attempt to assign offsets so that most of the consecutive accesses map to the same cache line. Our prefetching is done using a one entry line buffer [Wilson et al. 1996]. Consequently, many look-ups in D-cache reduce to incremental ones. This results in D-cache activity reduction and power savings. Our prefetcher requires both compiler and hardware support. In this paper, we provide implementation on the processor model close to ARM with small modification to the ISA. We tackle issues such as out-of-order commit, predication, and speculation through simple modifications to the processor
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