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16th acm sigplan International conference on Software language Engineering (SLE) as part of SPLASH conference

作者： Mosses, Peter D. Delft Univ Technol Delft Netherlands Swansea Univ Swansea Wales

ISBN: (纸本)9798400703966

Software language design and implementation often involve specifications written in various esoteric meta-languages. language workbenches generally include support for precise name-based navigation when browsing language specifications locally, but such support is lacking when browsing the same specifications online in code repositories. This paper presents a technique to support precise namebased navigation of language specifications in online repositories using ordinary web browsers. The idea is to generate hyperlinked twins: websites where verbatim copies of specification text are enhanced with hyperlinks between name references and declarations. By generating hyperlinks directly from the name binding analysis used internally in a language workbench, online navigation in hyperlinked twins is automatically consistent with local navigation. The presented technique has been implemented for the Spoofax language workbench, and used to generate hyperlinked twin websites from various language specifications in Spoofax meta-languages. However, the applicability of the technique is not limited to Spoofax, and developers of other language workbenches could presumably implement similar tooling, to make their language specifications more accessible to those who do not have the workbench installed.

关键词： code navigation hyperlinked twins language specifications meta-languages language workbenches

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vAttention: Dynamic Memory Management for Serving LLMs without PagedAttention 25

vAttention: Dynamic Memory Management for Serving LLMs witho...

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30th International conference on Architectural Support for programming languages and Operating Systems-ASPLOS

作者： Prabhu, Ramya Nayak, Ajay Mohan, Jayashree Ramjee, Ramchandran Panwar, Ashish Microsoft Res Bengaluru India Indian Inst Sci Bengaluru India

ISBN: (纸本)9798400706981

PagedAttention is a popular approach for dynamic memory allocation in PagedAttention serving systems. It enables on-demand allocation of GPU memory to mitigate KV cache fragmentation - a phenomenon that crippled the batch size (and consequently throughput) in prior systems. However, in trying to allocate physical memory at runtime, PagedAttention ends up changing the virtual memory layout of the KV cache from contiguous to non-contiguous. Such a design leads to non-trivial programming and performance overheads. We present vAttention - an approach that mitigates fragmentation in physical memory while retaining the virtual memory contiguity of the KV cache. We achieve this by decoupling the allocation of virtual and physical memory using CUDA virtual memory management APIs. We also introduce various LLM-specific optimizations to address the limitations of CUDA virtual memory support. Overall, vAttention is a simpler, portable, and performant alternative to PagedAttention: it supports various attention kernels out-of-the-box and improves LLM serving throughput by up to 1.23x compared to the use of PagedAttention-based kernels of FlashAttention-2 and FlashInfer.

关键词： Large language models KV cache fragmentation memory management

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A Virtual Machine for Higher-Order Reactors 8

A Virtual Machine for Higher-Order Reactors

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8th International conference on the Art, Science, and Engineering of programming (programming)

作者： Oeyen, Bjarno Nicolay, Jens De Meuter, Wolfgang Vrije Univ Brussel Brussels Belgium

ISBN: (纸本)9798400706349

We present the design of a Remus, a virtual machine for reactive (RP) programs - signal-based programs that react automatically to changes - that is currently under development. The design of Remus been tailored specifically for reactive programs: it has a dedicated instruction set and memory model that is compatible with the model of reactive programming. The virtual machine allows reactive programs to be evaluated without needing to compile them to native code, nor by running them on an existing (general-purpose) virtual machine that is not specific to RP. The model of the virtual machine makes it possible to reason over the various behavioural aspects of a reactive program, such as memory consumption, in a language-agnostic way. As an example, we propose a static analysis that aims to eliminate dynamic allocations that occur in dynamic reactive programs: i.e., programs where the dependencies between the signals that make up a program changes at run-time. We show that our virtual machine, supplemented by the results of the analysis, allows for (well-behaved) reactive programs to be evaluated in constant space (i.e. in bounded memory) even when dependencies change or new signals are created programmatically.

关键词： Reactive programming Virtual Machine Static Compilation Higher-Order programming

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CacheIR: The Benefits of a Structured Representation for Inline Caches 20

CacheIR: The Benefits of a Structured Representation for Inl...

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20th acm sigplan International conference on Managed programming languages and Runtimes (MPLR)

作者： De Mooij, Jan Gaudet, Matthew Ireland, Iain Henderson, Nathan Amaral, J. Nelson Mozilla Utrecht Netherlands Mozilla Toronto ON Canada Univ Alberta Edmonton AB Canada

ISBN: (纸本)9798400703805

Inline Caching is an important technique used to accelerate operations in dynamically typed language implementations by creating fast paths based on observed program behaviour. Most software stacks that support inline caching use low-level, often ad-hoc, Inline-Cache (ICs) data structures for code generation. This work presents CacheIR, a design for inline caching built entirely around an intermediate representation (IR) which: (i) simplifies the development of ICs by raising the abstraction level;and (ii) enables reusing compiled native code through IR matching techniques. Moreover, this work describesWarpBuilder, a novel design for a Just-In-Time (JIT) compiler front-end that directly generates type-specialized code by lowering the CacheIR contained in ICs;and Trial Inlining, an extension to the inline-caching system that allows for context-sensitive inlining of context-sensitive ICs. The combination of CacheIR and WarpBuilder have been powerful performance tools for the SpiderMonkey team, and have been key in providing improved performance with less security risk.

关键词： inline caching dynamically-typed programming languages just-in-time compilation

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Context-Free language Reachability via Skewed Tabulation

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PROCEEDINGS OF THE acm ON programming languageS-PacmPL 2024年第PLDI期8卷 1830-1853页

作者： Lei, Yuxiang Bossut, Camille Sui, Yulei Zhang, Qirun Univ New South Wales Sydney NSW Australia Georgia Inst Technol Atlanta GA USA

Context-free language reachability (CFL-reachability) is a prominent model for formulating program analysis problems. Almost all CFL-reachability algorithms are based on the Reps-Horwitz-Sagiv (RHS) tabulation. In essence, the RHS tabulation, based on normalized context-free grammars, is similar to the CYK algorithm for CFL-parsing. Consider a normalized rule S ::= A B and a CFL-reachability problem instance of computing S-edges in the input graph. The RHS tabulation obtains all summary edges (i.e., S-, A-, and B-edges) based on the grammar rules. However, many A- and B-edges are wasted because only a subset of those edges eventually contributes to generating S-edges in the input graph. This paper proposes a new tabulation strategy for speeding up CFL-reachability by eliminating wasted and unnecessary summary edges. We particularly focus on recursive nonterminals. Our key technical insight is that the wasted edge generations and insertions caused by recursive nonterminals can be avoided by modifying the parse trees either statically (by transforming the grammar) or dynamically (using a specialized online CFL-reachability solver). For example, if a recursive nonterminal B, generated by a rule B ::= B X, appears on the right-hand side of a rule S ::= A B, we can make S recursive (by introducing a new rule S ::= S X) and eliminate the original recursive rule (B ::= B X). Due to the rule S ::= S X, the shapes of the parse trees associated with the left-hand-side nonterminal S become more "skewed". Thus, we name our approach skewed tabulation for CFL-reachability. Skewed tabulation can significantly improve the scalability of CFL-reachability by reducing wasted and unnecessary summary edges. We have implemented skewed tabulation and applied the corresponding CFL-reachability algorithm to an alias analysis, a value-flow analysis, and a taint analysis. Our extensive evaluation based on SPEC 2017 benchmarks yields promising results. For the three client analyses, CFL-reacha

关键词： CFL-reachability tabulation schemes performance

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A Study of Real-World Data Races in Golang 2022

A Study of Real-World Data Races in Golang

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43rd acm sigplan International conference on programming language design and implementation (PLDI)

作者： Chabbi, Milind Ramanathan, Murali Krishna Uber Technol Inc Programming Syst Grp Sunnyvale CA 94086 USA

ISBN: (纸本)9781450392655

The concurrent programming literature is rich with tools and techniques for data race detection. Less, however, has been known about real-world, industry-scale deployment, experience, and insights about data races. Golang (Go for short) is a modern programming language that makes concurrency a first-class citizen. Go offers both message passing and shared memory for communicating among concurrent threads. Go is gaining popularity in modern microservice-based systems. Data races in Go stand in the face of its emerging popularity. In this paper, using our industrial codebase as an example, we demonstrate that Go developers embrace concurrency and show how the abundance of concurrency alongside language idioms and nuances make Go programs highly susceptible to data races. Google's Go distribution ships with a built-in dynamic data race detector based on ThreadSanitizer. However, dynamic race detectors pose scalability and flakiness challenges;we discuss various software engineering trade-offs to make this detector work effectively at scale. We have deployed this detector in Uber's 46 million lines of Go codebase hosting 2100 distinct microservices, found over 2000 data races, and fixed over 1000 data races, spanning 790 distinct code patches submitted by 210 unique developers over a six-month period. Based on a detailed investigation of these data race patterns in Go, we make seven high-level observations relating to the complex interplay between the Go language paradigm and data races.

关键词： Data race Golang Dynamic analysis

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Stepwise Debugging for Hardware Accelerators 2023

Stepwise Debugging for Hardware Accelerators

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28th acm International conference on Architectural Support for programming languages and Operating Systems (ASPLOS)

作者： Berlstein, Griffin Nigam, Rachit Gyurgyik, Christophe Sampson, Adrian Cornell Univ Ithaca NY 14853 USA

ISBN: (纸本)9781450399166

High-level programming models for hardware design let domain experts quickly produce specialized accelerators. However, tools for debugging these accelerators remain tied to low-level hardware description languages (HDLs). High-level descriptions contain control-flow information that is lost in HDL code. We describe Cider, a stepwise debugger that exploits this information to provide software-like debugging abstractions for languages that compile to hardware. Cider uses Calyx, an intermediate language for accelerator generators that preserves control information. Cider provides breakpoints, watchpoints, state inspection, and source-level position mapping. Using case studies that examine one new and two preexisting accelerator generators, we demonstrate howCider helps find and localize previously unreported bugs. By directly simulating a control-rich representation, Cider avoids wasting effort on inactive parts of the design and, despite being largely unoptimized, performs competitively with open-source HDL simulators.

关键词： Intermediate language Accelerator design Debugging Accelerator Simulation

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Realizing Persistent Signals in JavaScript 10

Realizing Persistent Signals in JavaScript

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10th acm sigplan International Workshop on Reactive and Event-Based languages and Systems (REBLS)

作者： Hidaka, Daichi Kamina, Tetsuo Oita Univ Oita Japan

ISBN: (纸本)9798400704000

Reactive programming enables declarative descriptions of dependencies between and computations throughout signals, an abstraction of time-varying values. Signals have been extended to persistent signals (an abstraction of time-varying values with their execution histories) to enable them to go back in time with any given time. Currently, this feature is only supported by SignalJ, an extension to Java with signals. This limits the use of persistent signals only within the Java-based applications. This is an undesirable restriction, because mechanisms used in realizing persistent signals are actually language-independent. To tackle this problem, we propose an implementation of persistent signals in JavaScript, which makes application areas of persistent signals broader, including Web-frontend. To realize persistent signals in JavaScript, seamless connections between JavaScript programs that run on restricted environments such as browsers and time-series databases that serve histories of persistent signals are required. It is also desirable to reuse existing JavaScript ecosystem. To address these problems, we design a relay-server-based architecture and realize persistent signals in JavaScript as a DSL library.

关键词： Distributed programming Relay-server-based architecture DSL library

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PDL A High-Level Hardware design language for Pipelined Processors 2022

PDL A High-Level Hardware Design Language for Pipelined Proc...

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43rd acm sigplan International conference on programming language design and implementation (PLDI)

作者： Zagieboylo, Drew Sherk, Charles Suh, Gookwon Edward Myers, Andrew C. Cornell Univ Dept Comp Sci Ithaca NY 14853 USA Cornell Univ Sch Elect & Comp Engn Ithaca NY 14853 USA

ISBN: (纸本)9781450392655

Processors are typically designed in Register Transfer Level (RTL) languages, which give designers low-level control over circuit structure and timing. To achieve good performance, processors are pipelined, with multiple instructions executing concurrently in different parts of the circuit. Thus even though processors implement a fundamentally sequential specification (the instruction set architecture), the implementation is highly concurrent. The interactions of multiple instructions-potentially speculative-can cause incorrect behavior. We present PDL, a novel hardware description language targeted at the construction of pipelined processors. PDL provides one-instruction-at-a-time semantics: the first language to enforce that the generated pipelined circuit has the same behavior as a sequential specification. This enforcement facilitates design-space exploration. Adding or removing pipeline stages, moving operations across stages, or otherwise changing pipeline structure normally requires careful analysis of bypass paths and stall logic;with PDL, this analysis is handled by the PDL compiler. At the same time, PDL still offers designers fine-grained control over performance-critical microarchitectural choices such as timing of operations, data forwarding, and speculation. We demonstrate PDL's expressive power and ease of design exploration by implementing several RISC-V cores with differing microarchitectures. Our results show that PDL does not impose significant performance or area overhead compared to a standard HDL.

关键词： Computer Architecture language design

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language-Integrated Query for Temporal Data 2022

Language-Integrated Query for Temporal Data

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21st acm sigplan International conference on Generative programming: Concepts and Experiences (GPCE)

作者： Fowler, Simon Galpin, Vashti Cheney, James Univ Glasgow Glasgow Lanark Scotland Univ Edinburgh Edinburgh Midlothian Scotland

ISBN: (纸本)9781450399203

Modern applications often manage time-varying data. Despite decades of research on temporal databases, which culminated in the addition of temporal data operations into the SQL:2011 standard, temporal data query and manipulation operations are unavailable in most mainstream database management systems, leaving developers with the unenviable task of implementing such functionality from scratch. In this paper, we extend language-integrated query to support writing temporal queries and updates in a uniform host language, with the language performing the required rewriting to emulate temporal capabilities automatically on any standard relational database. We introduce two core languages, lambda(TLINQ) and lambda(VLINQ), for manipulating transaction time and valid time data respectively, and formalise existing implementation strategies by giving provably correct semantics-preserving translations into a non-temporal core language, lambda(LINQ). We show how existing work on query normalisation supports a surprisingly simple implementation strategy for sequenced joins. We implement our approach in the Links programming language, and describe a non-trivial case study based on curating COVID-19 statistics.

关键词： language-integrated query temporal databases domain-specific languages multi-tier programming

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